#line 1 "../Core/Src/stm32g4xx_it.c"
 















 
 

 
#line 1 "../Core/Inc/main.h"
 
















 
 

 







 
#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h"

















 

 







 
#line 1 "../Core/Inc/stm32g4xx_hal_conf.h"
 
















 
 

 







 
 

 


 



   
 
 
 
 
 

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

 
 
 
#line 76 "../Core/Inc/stm32g4xx_hal_conf.h"

 


 
#line 110 "../Core/Inc/stm32g4xx_hal_conf.h"

 




 












 










 







 


 





 












 





 

 


 

#line 189 "../Core/Inc/stm32g4xx_hal_conf.h"

 



 
 

 




 



 


 

#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"















 

 







 
#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"

















 

 







 
#line 1 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h"


























 



 



 










 



 






 

#line 73 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h"



 
#line 85 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h"



 
#line 97 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h"



 



 

#line 1 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"






















 



 



 










 



 








 



 




 
typedef enum
{
 
  NonMaskableInt_IRQn         = -14,     
  HardFault_IRQn              = -13,     
  MemoryManagement_IRQn       = -12,     
  BusFault_IRQn               = -11,     
  UsageFault_IRQn             = -10,     
  SVCall_IRQn                 = -5,      
  DebugMonitor_IRQn           = -4,      
  PendSV_IRQn                 = -2,      
  SysTick_IRQn                = -1,      
 
  WWDG_IRQn                   = 0,       
  PVD_PVM_IRQn                = 1,       
  RTC_TAMP_LSECSS_IRQn        = 2,       
  RTC_WKUP_IRQn               = 3,       
  FLASH_IRQn                  = 4,       
  RCC_IRQn                    = 5,       
  EXTI0_IRQn                  = 6,       
  EXTI1_IRQn                  = 7,       
  EXTI2_IRQn                  = 8,       
  EXTI3_IRQn                  = 9,       
  EXTI4_IRQn                  = 10,      
  DMA1_Channel1_IRQn          = 11,      
  DMA1_Channel2_IRQn          = 12,      
  DMA1_Channel3_IRQn          = 13,      
  DMA1_Channel4_IRQn          = 14,      
  DMA1_Channel5_IRQn          = 15,      
  DMA1_Channel6_IRQn          = 16,      
  DMA1_Channel7_IRQn          = 17,      
  ADC1_2_IRQn                 = 18,      
  USB_HP_IRQn                 = 19,      
  USB_LP_IRQn                 = 20,      
  FDCAN1_IT0_IRQn             = 21,      
  FDCAN1_IT1_IRQn             = 22,      
  EXTI9_5_IRQn                = 23,      
  TIM1_BRK_TIM15_IRQn         = 24,      
  TIM1_UP_TIM16_IRQn          = 25,      
  TIM1_TRG_COM_TIM17_IRQn     = 26,      
  TIM1_CC_IRQn                = 27,      
  TIM2_IRQn                   = 28,      
  TIM3_IRQn                   = 29,      
  TIM4_IRQn                   = 30,      
  I2C1_EV_IRQn                = 31,      
  I2C1_ER_IRQn                = 32,      
  I2C2_EV_IRQn                = 33,      
  I2C2_ER_IRQn                = 34,      
  SPI1_IRQn                   = 35,      
  SPI2_IRQn                   = 36,      
  USART1_IRQn                 = 37,      
  USART2_IRQn                 = 38,      
  USART3_IRQn                 = 39,      
  EXTI15_10_IRQn              = 40,      
  RTC_Alarm_IRQn              = 41,      
  USBWakeUp_IRQn              = 42,      
  TIM8_BRK_IRQn               = 43,      
  TIM8_UP_IRQn                = 44,      
  TIM8_TRG_COM_IRQn           = 45,      
  TIM8_CC_IRQn                = 46,      
  ADC3_IRQn                   = 47,      
  FMC_IRQn                    = 48,      
  LPTIM1_IRQn                 = 49,      
  TIM5_IRQn                   = 50,      
  SPI3_IRQn                   = 51,      
  UART4_IRQn                  = 52,      
  UART5_IRQn                  = 53,      
  TIM6_DAC_IRQn               = 54,      
  TIM7_DAC_IRQn               = 55,      
  DMA2_Channel1_IRQn          = 56,      
  DMA2_Channel2_IRQn          = 57,      
  DMA2_Channel3_IRQn          = 58,      
  DMA2_Channel4_IRQn          = 59,      
  DMA2_Channel5_IRQn          = 60,      
  ADC4_IRQn                   = 61,      
  ADC5_IRQn                   = 62,      
  UCPD1_IRQn                  = 63,      
  COMP1_2_3_IRQn              = 64,      
  COMP4_5_6_IRQn              = 65,      
  COMP7_IRQn                  = 66,      
  HRTIM1_Master_IRQn          = 67,      
  HRTIM1_TIMA_IRQn            = 68,      
  HRTIM1_TIMB_IRQn            = 69,      
  HRTIM1_TIMC_IRQn            = 70,      
  HRTIM1_TIMD_IRQn            = 71,      
  HRTIM1_TIME_IRQn            = 72,      
  HRTIM1_FLT_IRQn             = 73,      
  HRTIM1_TIMF_IRQn            = 74,      
  CRS_IRQn                    = 75,      
  SAI1_IRQn                   = 76,      
  TIM20_BRK_IRQn              = 77,      
  TIM20_UP_IRQn               = 78,      
  TIM20_TRG_COM_IRQn          = 79,      
  TIM20_CC_IRQn               = 80,      
  FPU_IRQn                    = 81,      
  I2C4_EV_IRQn                = 82,      
  I2C4_ER_IRQn                = 83,      
  SPI4_IRQn                   = 84,      
  FDCAN2_IT0_IRQn             = 86,      
  FDCAN2_IT1_IRQn             = 87,      
  FDCAN3_IT0_IRQn             = 88,      
  FDCAN3_IT1_IRQn             = 89,      
  RNG_IRQn                    = 90,      
  LPUART1_IRQn                = 91,      
  I2C3_EV_IRQn                = 92,      
  I2C3_ER_IRQn                = 93,      
  DMAMUX_OVR_IRQn             = 94,      
  QUADSPI_IRQn                = 95,      
  DMA1_Channel8_IRQn          = 96,      
  DMA2_Channel6_IRQn          = 97,      
  DMA2_Channel7_IRQn          = 98,      
  DMA2_Channel8_IRQn          = 99,      
  CORDIC_IRQn                 = 100,     
  FMAC_IRQn                   = 101      
} IRQn_Type;



 

#line 1 "../Drivers/CMSIS/Include/core_cm4.h"
 




 
















 










#line 1 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdint.h"
 
 





 









     
#line 27 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdint.h"
     











#line 46 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdint.h"





 

     

     
typedef   signed          char int8_t;
typedef   signed short     int int16_t;
typedef   signed           int int32_t;
typedef   signed       __int64 int64_t;

     
typedef unsigned          char uint8_t;
typedef unsigned short     int uint16_t;
typedef unsigned           int uint32_t;
typedef unsigned       __int64 uint64_t;

     

     
     
typedef   signed          char int_least8_t;
typedef   signed short     int int_least16_t;
typedef   signed           int int_least32_t;
typedef   signed       __int64 int_least64_t;

     
typedef unsigned          char uint_least8_t;
typedef unsigned short     int uint_least16_t;
typedef unsigned           int uint_least32_t;
typedef unsigned       __int64 uint_least64_t;

     

     
typedef   signed           int int_fast8_t;
typedef   signed           int int_fast16_t;
typedef   signed           int int_fast32_t;
typedef   signed       __int64 int_fast64_t;

     
typedef unsigned           int uint_fast8_t;
typedef unsigned           int uint_fast16_t;
typedef unsigned           int uint_fast32_t;
typedef unsigned       __int64 uint_fast64_t;

     




typedef   signed           int intptr_t;
typedef unsigned           int uintptr_t;


     
typedef   signed     long long intmax_t;
typedef unsigned     long long uintmax_t;




     

     





     





     





     

     





     





     





     

     





     





     





     

     






     






     






     

     


     


     


     

     
#line 216 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdint.h"

     



     






     
    
 



#line 241 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdint.h"

     







     










     











#line 305 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stdint.h"






 
#line 35 "../Drivers/CMSIS/Include/core_cm4.h"

















 




 



 

#line 1 "../Drivers/CMSIS/Include/cmsis_version.h"
 




 
















 










 
#line 64 "../Drivers/CMSIS/Include/core_cm4.h"

 









 
#line 87 "../Drivers/CMSIS/Include/core_cm4.h"

#line 161 "../Drivers/CMSIS/Include/core_cm4.h"

#line 1 "../Drivers/CMSIS/Include/cmsis_compiler.h"
 




 
















 




#line 29 "../Drivers/CMSIS/Include/cmsis_compiler.h"



 
#line 1 "../Drivers/CMSIS/Include/cmsis_armcc.h"
 




 
















 









 













   
   

 




 
#line 110 "../Drivers/CMSIS/Include/cmsis_armcc.h"

 





















 



 





 
 






 
 





 
static __inline uint32_t __get_CONTROL(void)
{
  register uint32_t __regControl         __asm("control");
  return(__regControl);
}






 
static __inline void __set_CONTROL(uint32_t control)
{
  register uint32_t __regControl         __asm("control");
  __regControl = control;
}






 
static __inline uint32_t __get_IPSR(void)
{
  register uint32_t __regIPSR          __asm("ipsr");
  return(__regIPSR);
}






 
static __inline uint32_t __get_APSR(void)
{
  register uint32_t __regAPSR          __asm("apsr");
  return(__regAPSR);
}






 
static __inline uint32_t __get_xPSR(void)
{
  register uint32_t __regXPSR          __asm("xpsr");
  return(__regXPSR);
}






 
static __inline uint32_t __get_PSP(void)
{
  register uint32_t __regProcessStackPointer  __asm("psp");
  return(__regProcessStackPointer);
}






 
static __inline void __set_PSP(uint32_t topOfProcStack)
{
  register uint32_t __regProcessStackPointer  __asm("psp");
  __regProcessStackPointer = topOfProcStack;
}






 
static __inline uint32_t __get_MSP(void)
{
  register uint32_t __regMainStackPointer     __asm("msp");
  return(__regMainStackPointer);
}






 
static __inline void __set_MSP(uint32_t topOfMainStack)
{
  register uint32_t __regMainStackPointer     __asm("msp");
  __regMainStackPointer = topOfMainStack;
}






 
static __inline uint32_t __get_PRIMASK(void)
{
  register uint32_t __regPriMask         __asm("primask");
  return(__regPriMask);
}






 
static __inline void __set_PRIMASK(uint32_t priMask)
{
  register uint32_t __regPriMask         __asm("primask");
  __regPriMask = (priMask);
}









 







 







 
static __inline uint32_t  __get_BASEPRI(void)
{
  register uint32_t __regBasePri         __asm("basepri");
  return(__regBasePri);
}






 
static __inline void __set_BASEPRI(uint32_t basePri)
{
  register uint32_t __regBasePri         __asm("basepri");
  __regBasePri = (basePri & 0xFFU);
}







 
static __inline void __set_BASEPRI_MAX(uint32_t basePri)
{
  register uint32_t __regBasePriMax      __asm("basepri_max");
  __regBasePriMax = (basePri & 0xFFU);
}






 
static __inline uint32_t __get_FAULTMASK(void)
{
  register uint32_t __regFaultMask       __asm("faultmask");
  return(__regFaultMask);
}






 
static __inline void __set_FAULTMASK(uint32_t faultMask)
{
  register uint32_t __regFaultMask       __asm("faultmask");
  __regFaultMask = (faultMask & (uint32_t)1U);
}









 
static __inline uint32_t __get_FPSCR(void)
{


  register uint32_t __regfpscr         __asm("fpscr");
  return(__regfpscr);



}






 
static __inline void __set_FPSCR(uint32_t fpscr)
{


  register uint32_t __regfpscr         __asm("fpscr");
  __regfpscr = (fpscr);



}


 


 



 




 






 







 






 








 










 










 






                  





 








 

__attribute__((section(".rev16_text"))) static __inline __asm uint32_t __REV16(uint32_t value)
{
  rev16 r0, r0
  bx lr
}








 

__attribute__((section(".revsh_text"))) static __inline __asm int16_t __REVSH(int16_t value)
{
  revsh r0, r0
  bx lr
}









 









 








 
#line 561 "../Drivers/CMSIS/Include/cmsis_armcc.h"







 











 












 












 














 














 














 










 









 









 









 

__attribute__((section(".rrx_text"))) static __inline __asm uint32_t __RRX(uint32_t value)
{
  rrx r0, r0
  bx lr
}








 








 








 








 








 








 


#line 809 "../Drivers/CMSIS/Include/cmsis_armcc.h"

   


 



 



#line 880 "../Drivers/CMSIS/Include/cmsis_armcc.h"











 


#line 35 "../Drivers/CMSIS/Include/cmsis_compiler.h"




 
#line 280 "../Drivers/CMSIS/Include/cmsis_compiler.h"




#line 163 "../Drivers/CMSIS/Include/core_cm4.h"

















 
#line 207 "../Drivers/CMSIS/Include/core_cm4.h"

 






 
#line 223 "../Drivers/CMSIS/Include/core_cm4.h"

 




 













 



 






 



 
typedef union
{
  struct
  {
    uint32_t _reserved0:16;               
    uint32_t GE:4;                        
    uint32_t _reserved1:7;                
    uint32_t Q:1;                         
    uint32_t V:1;                         
    uint32_t C:1;                         
    uint32_t Z:1;                         
    uint32_t N:1;                         
  } b;                                    
  uint32_t w;                             
} APSR_Type;

 





















 
typedef union
{
  struct
  {
    uint32_t ISR:9;                       
    uint32_t _reserved0:23;               
  } b;                                    
  uint32_t w;                             
} IPSR_Type;

 






 
typedef union
{
  struct
  {
    uint32_t ISR:9;                       
    uint32_t _reserved0:1;                
    uint32_t ICI_IT_1:6;                  
    uint32_t GE:4;                        
    uint32_t _reserved1:4;                
    uint32_t T:1;                         
    uint32_t ICI_IT_2:2;                  
    uint32_t Q:1;                         
    uint32_t V:1;                         
    uint32_t C:1;                         
    uint32_t Z:1;                         
    uint32_t N:1;                         
  } b;                                    
  uint32_t w;                             
} xPSR_Type;

 

































 
typedef union
{
  struct
  {
    uint32_t nPRIV:1;                     
    uint32_t SPSEL:1;                     
    uint32_t FPCA:1;                      
    uint32_t _reserved0:29;               
  } b;                                    
  uint32_t w;                             
} CONTROL_Type;

 









 







 



 
typedef struct
{
  volatile uint32_t ISER[8U];                
        uint32_t RESERVED0[24U];
  volatile uint32_t ICER[8U];                
        uint32_t RESERVED1[24U];
  volatile uint32_t ISPR[8U];                
        uint32_t RESERVED2[24U];
  volatile uint32_t ICPR[8U];                
        uint32_t RESERVED3[24U];
  volatile uint32_t IABR[8U];                
        uint32_t RESERVED4[56U];
  volatile uint8_t  IP[240U];                
        uint32_t RESERVED5[644U];
  volatile  uint32_t STIR;                    
}  NVIC_Type;

 



 







 



 
typedef struct
{
  volatile const  uint32_t CPUID;                   
  volatile uint32_t ICSR;                    
  volatile uint32_t VTOR;                    
  volatile uint32_t AIRCR;                   
  volatile uint32_t SCR;                     
  volatile uint32_t CCR;                     
  volatile uint8_t  SHP[12U];                
  volatile uint32_t SHCSR;                   
  volatile uint32_t CFSR;                    
  volatile uint32_t HFSR;                    
  volatile uint32_t DFSR;                    
  volatile uint32_t MMFAR;                   
  volatile uint32_t BFAR;                    
  volatile uint32_t AFSR;                    
  volatile const  uint32_t PFR[2U];                 
  volatile const  uint32_t DFR;                     
  volatile const  uint32_t ADR;                     
  volatile const  uint32_t MMFR[4U];                
  volatile const  uint32_t ISAR[5U];                
        uint32_t RESERVED0[5U];
  volatile uint32_t CPACR;                   
} SCB_Type;

 















 






























 



 





















 









 


















 










































 









 


















 





















 


















 









 















 







 



 
typedef struct
{
        uint32_t RESERVED0[1U];
  volatile const  uint32_t ICTR;                    
  volatile uint32_t ACTLR;                   
} SCnSCB_Type;

 



 















 







 



 
typedef struct
{
  volatile uint32_t CTRL;                    
  volatile uint32_t LOAD;                    
  volatile uint32_t VAL;                     
  volatile const  uint32_t CALIB;                   
} SysTick_Type;

 












 



 



 









 







 



 
typedef struct
{
  volatile  union
  {
    volatile  uint8_t    u8;                  
    volatile  uint16_t   u16;                 
    volatile  uint32_t   u32;                 
  }  PORT [32U];                          
        uint32_t RESERVED0[864U];
  volatile uint32_t TER;                     
        uint32_t RESERVED1[15U];
  volatile uint32_t TPR;                     
        uint32_t RESERVED2[15U];
  volatile uint32_t TCR;                     
        uint32_t RESERVED3[32U];
        uint32_t RESERVED4[43U];
  volatile  uint32_t LAR;                     
  volatile const  uint32_t LSR;                     
        uint32_t RESERVED5[6U];
  volatile const  uint32_t PID4;                    
  volatile const  uint32_t PID5;                    
  volatile const  uint32_t PID6;                    
  volatile const  uint32_t PID7;                    
  volatile const  uint32_t PID0;                    
  volatile const  uint32_t PID1;                    
  volatile const  uint32_t PID2;                    
  volatile const  uint32_t PID3;                    
  volatile const  uint32_t CID0;                    
  volatile const  uint32_t CID1;                    
  volatile const  uint32_t CID2;                    
  volatile const  uint32_t CID3;                    
} ITM_Type;

 



 



























 









   







 



 
typedef struct
{
  volatile uint32_t CTRL;                    
  volatile uint32_t CYCCNT;                  
  volatile uint32_t CPICNT;                  
  volatile uint32_t EXCCNT;                  
  volatile uint32_t SLEEPCNT;                
  volatile uint32_t LSUCNT;                  
  volatile uint32_t FOLDCNT;                 
  volatile const  uint32_t PCSR;                    
  volatile uint32_t COMP0;                   
  volatile uint32_t MASK0;                   
  volatile uint32_t FUNCTION0;               
        uint32_t RESERVED0[1U];
  volatile uint32_t COMP1;                   
  volatile uint32_t MASK1;                   
  volatile uint32_t FUNCTION1;               
        uint32_t RESERVED1[1U];
  volatile uint32_t COMP2;                   
  volatile uint32_t MASK2;                   
  volatile uint32_t FUNCTION2;               
        uint32_t RESERVED2[1U];
  volatile uint32_t COMP3;                   
  volatile uint32_t MASK3;                   
  volatile uint32_t FUNCTION3;               
} DWT_Type;

 






















































 



 



 



 



 



 



 



























   







 



 
typedef struct
{
  volatile const  uint32_t SSPSR;                   
  volatile uint32_t CSPSR;                   
        uint32_t RESERVED0[2U];
  volatile uint32_t ACPR;                    
        uint32_t RESERVED1[55U];
  volatile uint32_t SPPR;                    
        uint32_t RESERVED2[131U];
  volatile const  uint32_t FFSR;                    
  volatile uint32_t FFCR;                    
  volatile const  uint32_t FSCR;                    
        uint32_t RESERVED3[759U];
  volatile const  uint32_t TRIGGER;                 
  volatile const  uint32_t FIFO0;                   
  volatile const  uint32_t ITATBCTR2;               
        uint32_t RESERVED4[1U];
  volatile const  uint32_t ITATBCTR0;               
  volatile const  uint32_t FIFO1;                   
  volatile uint32_t ITCTRL;                  
        uint32_t RESERVED5[39U];
  volatile uint32_t CLAIMSET;                
  volatile uint32_t CLAIMCLR;                
        uint32_t RESERVED7[8U];
  volatile const  uint32_t DEVID;                   
  volatile const  uint32_t DEVTYPE;                 
} TPI_Type;

 



 



 












 






 



 





















 






 





















 






 



 


















 






   








 



 
typedef struct
{
  volatile const  uint32_t TYPE;                    
  volatile uint32_t CTRL;                    
  volatile uint32_t RNR;                     
  volatile uint32_t RBAR;                    
  volatile uint32_t RASR;                    
  volatile uint32_t RBAR_A1;                 
  volatile uint32_t RASR_A1;                 
  volatile uint32_t RBAR_A2;                 
  volatile uint32_t RASR_A2;                 
  volatile uint32_t RBAR_A3;                 
  volatile uint32_t RASR_A3;                 
} MPU_Type;



 









 









 



 









 






























 








 



 
typedef struct
{
        uint32_t RESERVED0[1U];
  volatile uint32_t FPCCR;                   
  volatile uint32_t FPCAR;                   
  volatile uint32_t FPDSCR;                  
  volatile const  uint32_t MVFR0;                   
  volatile const  uint32_t MVFR1;                   
  volatile const  uint32_t MVFR2;                   
} FPU_Type;

 



























 



 












 
























 












 




 







 



 
typedef struct
{
  volatile uint32_t DHCSR;                   
  volatile  uint32_t DCRSR;                   
  volatile uint32_t DCRDR;                   
  volatile uint32_t DEMCR;                   
} CoreDebug_Type;

 




































 






 







































 







 






 







 


 







 

 
#line 1553 "../Drivers/CMSIS/Include/core_cm4.h"

#line 1562 "../Drivers/CMSIS/Include/core_cm4.h"









 










 


 



 





 

#line 1616 "../Drivers/CMSIS/Include/core_cm4.h"

#line 1626 "../Drivers/CMSIS/Include/core_cm4.h"




 
#line 1637 "../Drivers/CMSIS/Include/core_cm4.h"










 
static __inline void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
  uint32_t reg_value;
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);              

  reg_value  =  ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->AIRCR;                                                    
  reg_value &= ~((uint32_t)((0xFFFFUL << 16U) | (7UL << 8U)));  
  reg_value  =  (reg_value                                   |
                ((uint32_t)0x5FAUL << 16U) |
                (PriorityGroupTmp << 8U)  );               
  ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->AIRCR =  reg_value;
}






 
static __inline uint32_t __NVIC_GetPriorityGrouping(void)
{
  return ((uint32_t)((((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->AIRCR & (7UL << 8U)) >> 8U));
}







 
static __inline void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
  {
    __memory_changed();
    ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    __memory_changed();
  }
}









 
static __inline uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
  {
    return((uint32_t)(((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
  }
  else
  {
    return(0U);
  }
}







 
static __inline void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
  {
    ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U);
    do { __schedule_barrier(); __isb(0xF); __schedule_barrier(); } while (0U);
  }
}









 
static __inline uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
  {
    return((uint32_t)(((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
  }
  else
  {
    return(0U);
  }
}







 
static __inline void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
  {
    ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
  }
}







 
static __inline void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
  {
    ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
  }
}









 
static __inline uint32_t __NVIC_GetActive(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
  {
    return((uint32_t)(((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
  }
  else
  {
    return(0U);
  }
}










 
static __inline void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
  if ((int32_t)(IRQn) >= 0)
  {
    ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - 4U)) & (uint32_t)0xFFUL);
  }
  else
  {
    ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - 4U)) & (uint32_t)0xFFUL);
  }
}










 
static __inline uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{

  if ((int32_t)(IRQn) >= 0)
  {
    return(((uint32_t)((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IP[((uint32_t)IRQn)]               >> (8U - 4U)));
  }
  else
  {
    return(((uint32_t)((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - 4U)));
  }
}












 
static __inline uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);    
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(4U)) ? (uint32_t)(4U) : (uint32_t)(7UL - PriorityGroupTmp);
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(4U)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(4U));

  return (
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
         );
}












 
static __inline void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);    
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(4U)) ? (uint32_t)(4U) : (uint32_t)(7UL - PriorityGroupTmp);
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(4U)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(4U));

  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
}










 
static __inline void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
  uint32_t vectors = (uint32_t )((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->VTOR;
  (* (int *) (vectors + ((int32_t)IRQn + 16) * 4)) = vector;
   
}









 
static __inline uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
  uint32_t vectors = (uint32_t )((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->VTOR;
  return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + 16) * 4));
}





 
__declspec(noreturn) static __inline void __NVIC_SystemReset(void)
{
  do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U);                                                          
 
  ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->AIRCR  = (uint32_t)((0x5FAUL << 16U)    |
                           (((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->AIRCR & (7UL << 8U)) |
                            (1UL << 2U)    );          
  do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U);                                                           

  for(;;)                                                            
  {
    __nop();
  }
}

 


 



#line 1 "../Drivers/CMSIS/Include/mpu_armv7.h"





 
















 
 





 



#line 62 "../Drivers/CMSIS/Include/mpu_armv7.h"

#line 69 "../Drivers/CMSIS/Include/mpu_armv7.h"





 












   














 
#line 110 "../Drivers/CMSIS/Include/mpu_armv7.h"












                          









  










  












  




 




 




 




 





 
typedef struct {
  uint32_t RBAR; 
  uint32_t RASR; 
} ARM_MPU_Region_t;
    


 
static __inline void ARM_MPU_Enable(uint32_t MPU_Control)
{
  ((MPU_Type *) ((0xE000E000UL) + 0x0D90UL) )->CTRL = MPU_Control | (1UL );

  ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHCSR |= (1UL << 16U);

  do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U);
  do { __schedule_barrier(); __isb(0xF); __schedule_barrier(); } while (0U);
}


 
static __inline void ARM_MPU_Disable(void)
{
  do { __schedule_barrier(); __dmb(0xF); __schedule_barrier(); } while (0U);

  ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHCSR &= ~(1UL << 16U);

  ((MPU_Type *) ((0xE000E000UL) + 0x0D90UL) )->CTRL  &= ~(1UL );
}



 
static __inline void ARM_MPU_ClrRegion(uint32_t rnr)
{
  ((MPU_Type *) ((0xE000E000UL) + 0x0D90UL) )->RNR = rnr;
  ((MPU_Type *) ((0xE000E000UL) + 0x0D90UL) )->RASR = 0U;
}




    
static __inline void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
  ((MPU_Type *) ((0xE000E000UL) + 0x0D90UL) )->RBAR = rbar;
  ((MPU_Type *) ((0xE000E000UL) + 0x0D90UL) )->RASR = rasr;
}





    
static __inline void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
  ((MPU_Type *) ((0xE000E000UL) + 0x0D90UL) )->RNR = rnr;
  ((MPU_Type *) ((0xE000E000UL) + 0x0D90UL) )->RBAR = rbar;
  ((MPU_Type *) ((0xE000E000UL) + 0x0D90UL) )->RASR = rasr;
}





 
static __inline void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __restrict src, uint32_t len)
{
  uint32_t i;
  for (i = 0U; i < len; ++i) 
  {
    dst[i] = src[i];
  }
}




 
static __inline void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
{
  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
  while (cnt > 4U) {
    ARM_MPU_OrderedMemcpy(&(((MPU_Type *) ((0xE000E000UL) + 0x0D90UL) )->RBAR), &(table->RBAR), 4U*rowWordSize);
    table += 4U;
    cnt -= 4U;
  }
  ARM_MPU_OrderedMemcpy(&(((MPU_Type *) ((0xE000E000UL) + 0x0D90UL) )->RBAR), &(table->RBAR), cnt*rowWordSize);
}

#line 1956 "../Drivers/CMSIS/Include/core_cm4.h"




 





 








 
static __inline uint32_t SCB_GetFPUType(void)
{
  uint32_t mvfr0;

  mvfr0 = ((FPU_Type *) ((0xE000E000UL) + 0x0F30UL) )->MVFR0;
  if      ((mvfr0 & ((0xFUL << 4U) | (0xFUL << 8U))) == 0x020U)
  {
    return 1U;            
  }
  else
  {
    return 0U;            
  }
}


 



 





 













 
static __inline uint32_t SysTick_Config(uint32_t ticks)
{
  if ((ticks - 1UL) > (0xFFFFFFUL ))
  {
    return (1UL);                                                    
  }

  ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->LOAD  = (uint32_t)(ticks - 1UL);                          
  __NVIC_SetPriority (SysTick_IRQn, (1UL << 4U) - 1UL);  
  ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->VAL   = 0UL;                                              
  ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->CTRL  = (1UL << 2U) |
                   (1UL << 1U)   |
                   (1UL );                          
  return (0UL);                                                      
}



 



 





 

extern volatile int32_t ITM_RxBuffer;                               










 
static __inline uint32_t ITM_SendChar (uint32_t ch)
{
  if (((((ITM_Type *) (0xE0000000UL) )->TCR & (1UL )) != 0UL) &&       
      ((((ITM_Type *) (0xE0000000UL) )->TER & 1UL               ) != 0UL)   )      
  {
    while (((ITM_Type *) (0xE0000000UL) )->PORT[0U].u32 == 0UL)
    {
      __nop();
    }
    ((ITM_Type *) (0xE0000000UL) )->PORT[0U].u8 = (uint8_t)ch;
  }
  return (ch);
}







 
static __inline int32_t ITM_ReceiveChar (void)
{
  int32_t ch = -1;                            

  if (ITM_RxBuffer != ((int32_t)0x5AA55AA5U))
  {
    ch = ITM_RxBuffer;
    ITM_RxBuffer = ((int32_t)0x5AA55AA5U);        
  }

  return (ch);
}







 
static __inline int32_t ITM_CheckChar (void)
{

  if (ITM_RxBuffer == ((int32_t)0x5AA55AA5U))
  {
    return (0);                               
  }
  else
  {
    return (1);                               
  }
}

 










#line 186 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"
#line 1 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h"
















 



 



 



 









 



 




 
  






 
extern uint32_t SystemCoreClock;             

extern const uint8_t  AHBPrescTable[16];     
extern const uint8_t  APBPrescTable[8];      



 



 



 



 



 



 

extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);


 









 



 
#line 187 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"
#line 188 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"



 



 

typedef struct
{
  volatile uint32_t ISR;           
  volatile uint32_t IER;           
  volatile uint32_t CR;            
  volatile uint32_t CFGR;          
  volatile uint32_t CFGR2;         
  volatile uint32_t SMPR1;         
  volatile uint32_t SMPR2;         
       uint32_t RESERVED1;     
  volatile uint32_t TR1;           
  volatile uint32_t TR2;           
  volatile uint32_t TR3;           
       uint32_t RESERVED2;     
  volatile uint32_t SQR1;          
  volatile uint32_t SQR2;          
  volatile uint32_t SQR3;          
  volatile uint32_t SQR4;          
  volatile uint32_t DR;            
       uint32_t RESERVED3;     
       uint32_t RESERVED4;     
  volatile uint32_t JSQR;          
       uint32_t RESERVED5[4];  
  volatile uint32_t OFR1;          
  volatile uint32_t OFR2;          
  volatile uint32_t OFR3;          
  volatile uint32_t OFR4;          
       uint32_t RESERVED6[4];  
  volatile uint32_t JDR1;          
  volatile uint32_t JDR2;          
  volatile uint32_t JDR3;          
  volatile uint32_t JDR4;          
       uint32_t RESERVED7[4];  
  volatile uint32_t AWD2CR;        
  volatile uint32_t AWD3CR;        
       uint32_t RESERVED8;     
       uint32_t RESERVED9;     
  volatile uint32_t DIFSEL;        
  volatile uint32_t CALFACT;       
       uint32_t RESERVED10[2]; 
  volatile uint32_t GCOMP;         
} ADC_TypeDef;

typedef struct
{
  volatile uint32_t CSR;           
  uint32_t      RESERVED1;     
  volatile uint32_t CCR;           
  volatile uint32_t CDR;           
} ADC_Common_TypeDef;



 

typedef struct
{
  volatile uint32_t CREL;          
  volatile uint32_t ENDN;          
       uint32_t RESERVED1;     
  volatile uint32_t DBTP;          
  volatile uint32_t TEST;          
  volatile uint32_t RWD;           
  volatile uint32_t CCCR;          
  volatile uint32_t NBTP;          
  volatile uint32_t TSCC;          
  volatile uint32_t TSCV;          
  volatile uint32_t TOCC;          
  volatile uint32_t TOCV;          
       uint32_t RESERVED2[4];  
  volatile uint32_t ECR;           
  volatile uint32_t PSR;           
  volatile uint32_t TDCR;          
       uint32_t RESERVED3;     
  volatile uint32_t IR;            
  volatile uint32_t IE;            
  volatile uint32_t ILS;           
  volatile uint32_t ILE;           
       uint32_t RESERVED4[8];  
  volatile uint32_t RXGFC;         
  volatile uint32_t XIDAM;         
  volatile uint32_t HPMS;          
       uint32_t RESERVED5;     
  volatile uint32_t RXF0S;         
  volatile uint32_t RXF0A;         
  volatile uint32_t RXF1S;         
  volatile uint32_t RXF1A;         
       uint32_t RESERVED6[8];  
  volatile uint32_t TXBC;          
  volatile uint32_t TXFQS;         
  volatile uint32_t TXBRP;         
  volatile uint32_t TXBAR;         
  volatile uint32_t TXBCR;         
  volatile uint32_t TXBTO;         
  volatile uint32_t TXBCF;         
  volatile uint32_t TXBTIE;        
  volatile uint32_t TXBCIE;        
  volatile uint32_t TXEFS;         
  volatile uint32_t TXEFA;         
} FDCAN_GlobalTypeDef;



 

typedef struct
{
  volatile uint32_t CKDIV;         
} FDCAN_Config_TypeDef;



 

typedef struct
{
  volatile uint32_t CSR;          
} COMP_TypeDef;



 

typedef struct
{
  volatile uint32_t DR;           
  volatile uint32_t IDR;          
  volatile uint32_t CR;           
  uint32_t      RESERVED0;    
  volatile uint32_t INIT;         
  volatile uint32_t POL;          
} CRC_TypeDef;



 
typedef struct
{
  volatile uint32_t CR;           
  volatile uint32_t CFGR;         
  volatile uint32_t ISR;          
  volatile uint32_t ICR;          
} CRS_TypeDef;



 

typedef struct
{
  volatile uint32_t CR;           
  volatile uint32_t SWTRIGR;      
  volatile uint32_t DHR12R1;      
  volatile uint32_t DHR12L1;      
  volatile uint32_t DHR8R1;       
  volatile uint32_t DHR12R2;      
  volatile uint32_t DHR12L2;      
  volatile uint32_t DHR8R2;       
  volatile uint32_t DHR12RD;      
  volatile uint32_t DHR12LD;      
  volatile uint32_t DHR8RD;       
  volatile uint32_t DOR1;         
  volatile uint32_t DOR2;         
  volatile uint32_t SR;           
  volatile uint32_t CCR;          
  volatile uint32_t MCR;          
  volatile uint32_t SHSR1;        
  volatile uint32_t SHSR2;        
  volatile uint32_t SHHR;         
  volatile uint32_t SHRR;         
  volatile uint32_t RESERVED[2];
  volatile uint32_t STR1;         
  volatile uint32_t STR2;         
  volatile uint32_t STMODR;       
} DAC_TypeDef;



 

typedef struct
{
  volatile uint32_t IDCODE;       
  volatile uint32_t CR;           
  volatile uint32_t APB1FZR1;     
  volatile uint32_t APB1FZR2;     
  volatile uint32_t APB2FZ;       
} DBGMCU_TypeDef;



 

typedef struct
{
  volatile uint32_t CCR;          
  volatile uint32_t CNDTR;        
  volatile uint32_t CPAR;         
  volatile uint32_t CMAR;         
} DMA_Channel_TypeDef;

typedef struct
{
  volatile uint32_t ISR;          
  volatile uint32_t IFCR;         
} DMA_TypeDef;



 

typedef struct
{
  volatile uint32_t   CCR;        
}DMAMUX_Channel_TypeDef;

typedef struct
{
  volatile uint32_t   CSR;       
  volatile uint32_t   CFR;       
}DMAMUX_ChannelStatus_TypeDef;

typedef struct
{
  volatile uint32_t   RGCR;         
}DMAMUX_RequestGen_TypeDef;

typedef struct
{
  volatile uint32_t   RGSR;         
  volatile uint32_t   RGCFR;         
}DMAMUX_RequestGenStatus_TypeDef;



 

typedef struct
{
  volatile uint32_t IMR1;         
  volatile uint32_t EMR1;         
  volatile uint32_t RTSR1;        
  volatile uint32_t FTSR1;        
  volatile uint32_t SWIER1;       
  volatile uint32_t PR1;          
  uint32_t      RESERVED1;    
  uint32_t      RESERVED2;    
  volatile uint32_t IMR2;         
  volatile uint32_t EMR2;         
  volatile uint32_t RTSR2;        
  volatile uint32_t FTSR2;        
  volatile uint32_t SWIER2;       
  volatile uint32_t PR2;          
} EXTI_TypeDef;



 

typedef struct
{
  volatile uint32_t ACR;               
  volatile uint32_t PDKEYR;            
  volatile uint32_t KEYR;              
  volatile uint32_t OPTKEYR;           
  volatile uint32_t SR;                
  volatile uint32_t CR;                
  volatile uint32_t ECCR;              
       uint32_t RESERVED1;         
  volatile uint32_t OPTR;              
  volatile uint32_t PCROP1SR;          
  volatile uint32_t PCROP1ER;          
  volatile uint32_t WRP1AR;            
  volatile uint32_t WRP1BR;            
       uint32_t RESERVED2[4];      
  volatile uint32_t PCROP2SR;          
  volatile uint32_t PCROP2ER;          
  volatile uint32_t WRP2AR;            
  volatile uint32_t WRP2BR;            
       uint32_t RESERVED3[7];      
  volatile uint32_t SEC1R;             
  volatile uint32_t SEC2R;             
} FLASH_TypeDef;



 
typedef struct
{
  volatile uint32_t X1BUFCFG;         
  volatile uint32_t X2BUFCFG;         
  volatile uint32_t YBUFCFG;          
  volatile uint32_t PARAM;            
  volatile uint32_t CR;               
  volatile uint32_t SR;               
  volatile uint32_t WDATA;            
  volatile uint32_t RDATA;            
} FMAC_TypeDef;



 

typedef struct
{
  volatile uint32_t BTCR[8];      
  volatile uint32_t PCSCNTR;      
} FMC_Bank1_TypeDef;



 

typedef struct
{
  volatile uint32_t BWTR[7];      
} FMC_Bank1E_TypeDef;



 

typedef struct
{
  volatile uint32_t PCR;         
  volatile uint32_t SR;          
  volatile uint32_t PMEM;        
  volatile uint32_t PATT;        
  uint32_t      RESERVED0;   
  volatile uint32_t ECCR;        
} FMC_Bank3_TypeDef;



 

typedef struct
{
  volatile uint32_t MODER;        
  volatile uint32_t OTYPER;       
  volatile uint32_t OSPEEDR;      
  volatile uint32_t PUPDR;        
  volatile uint32_t IDR;          
  volatile uint32_t ODR;          
  volatile uint32_t BSRR;         
  volatile uint32_t LCKR;         
  volatile uint32_t AFR[2];       
  volatile uint32_t BRR;          
} GPIO_TypeDef;



 

typedef struct
{
  volatile uint32_t CR1;          
  volatile uint32_t CR2;          
  volatile uint32_t OAR1;         
  volatile uint32_t OAR2;         
  volatile uint32_t TIMINGR;      
  volatile uint32_t TIMEOUTR;     
  volatile uint32_t ISR;          
  volatile uint32_t ICR;          
  volatile uint32_t PECR;         
  volatile uint32_t RXDR;         
  volatile uint32_t TXDR;         
} I2C_TypeDef;



 

typedef struct
{
  volatile uint32_t KR;           
  volatile uint32_t PR;           
  volatile uint32_t RLR;          
  volatile uint32_t SR;           
  volatile uint32_t WINR;         
} IWDG_TypeDef;



 

typedef struct
{
  volatile uint32_t ISR;               
  volatile uint32_t ICR;               
  volatile uint32_t IER;               
  volatile uint32_t CFGR;              
  volatile uint32_t CR;                
  volatile uint32_t CMP;               
  volatile uint32_t ARR;               
  volatile uint32_t CNT;               
  volatile uint32_t OR;                
} LPTIM_TypeDef;



 

typedef struct
{
  volatile uint32_t CSR;            
  volatile uint32_t RESERVED[5];    
  volatile uint32_t TCMR;           
} OPAMP_TypeDef;



 

typedef struct
{
  volatile uint32_t CR1;       
  volatile uint32_t CR2;       
  volatile uint32_t CR3;       
  volatile uint32_t CR4;       
  volatile uint32_t SR1;       
  volatile uint32_t SR2;       
  volatile uint32_t SCR;       
  uint32_t RESERVED;       
  volatile uint32_t PUCRA;     
  volatile uint32_t PDCRA;     
  volatile uint32_t PUCRB;     
  volatile uint32_t PDCRB;     
  volatile uint32_t PUCRC;     
  volatile uint32_t PDCRC;     
  volatile uint32_t PUCRD;     
  volatile uint32_t PDCRD;     
  volatile uint32_t PUCRE;     
  volatile uint32_t PDCRE;     
  volatile uint32_t PUCRF;     
  volatile uint32_t PDCRF;     
  volatile uint32_t PUCRG;     
  volatile uint32_t PDCRG;     
  uint32_t RESERVED1[10];  
  volatile uint32_t CR5;       
} PWR_TypeDef;



 

typedef struct
{
  volatile uint32_t CR;           
  volatile uint32_t DCR;          
  volatile uint32_t SR;           
  volatile uint32_t FCR;          
  volatile uint32_t DLR;          
  volatile uint32_t CCR;          
  volatile uint32_t AR;           
  volatile uint32_t ABR;          
  volatile uint32_t DR;           
  volatile uint32_t PSMKR;        
  volatile uint32_t PSMAR;        
  volatile uint32_t PIR;          
  volatile uint32_t LPTR;         
} QUADSPI_TypeDef;



 

typedef struct
{
  volatile uint32_t CR;           
  volatile uint32_t ICSCR;        
  volatile uint32_t CFGR;         
  volatile uint32_t PLLCFGR;      
  uint32_t      RESERVED0;    
  uint32_t      RESERVED1;    
  volatile uint32_t CIER;         
  volatile uint32_t CIFR;         
  volatile uint32_t CICR;         
  uint32_t      RESERVED2;    
  volatile uint32_t AHB1RSTR;     
  volatile uint32_t AHB2RSTR;     
  volatile uint32_t AHB3RSTR;     
  uint32_t      RESERVED3;    
  volatile uint32_t APB1RSTR1;    
  volatile uint32_t APB1RSTR2;    
  volatile uint32_t APB2RSTR;     
  uint32_t      RESERVED4;    
  volatile uint32_t AHB1ENR;      
  volatile uint32_t AHB2ENR;      
  volatile uint32_t AHB3ENR;      
  uint32_t      RESERVED5;    
  volatile uint32_t APB1ENR1;     
  volatile uint32_t APB1ENR2;     
  volatile uint32_t APB2ENR;      
  uint32_t      RESERVED6;    
  volatile uint32_t AHB1SMENR;    
  volatile uint32_t AHB2SMENR;    
  volatile uint32_t AHB3SMENR;    
  uint32_t      RESERVED7;    
  volatile uint32_t APB1SMENR1;   
  volatile uint32_t APB1SMENR2;   
  volatile uint32_t APB2SMENR;    
  uint32_t      RESERVED8;    
  volatile uint32_t CCIPR;        
  uint32_t      RESERVED9;    
  volatile uint32_t BDCR;         
  volatile uint32_t CSR;          
  volatile uint32_t CRRCR;        
  volatile uint32_t CCIPR2;       
} RCC_TypeDef;



 


 







typedef struct
{
  volatile uint32_t TR;           
  volatile uint32_t DR;           
  volatile uint32_t SSR;          
  volatile uint32_t ICSR;         
  volatile uint32_t PRER;         
  volatile uint32_t WUTR;         
  volatile uint32_t CR;           
       uint32_t RESERVED0;    
       uint32_t RESERVED1;    
  volatile uint32_t WPR;          
  volatile uint32_t CALR;         
  volatile uint32_t SHIFTR;       
  volatile uint32_t TSTR;         
  volatile uint32_t TSDR;         
  volatile uint32_t TSSSR;        
       uint32_t RESERVED2;    
  volatile uint32_t ALRMAR;       
  volatile uint32_t ALRMASSR;     
  volatile uint32_t ALRMBR;       
  volatile uint32_t ALRMBSSR;     
  volatile uint32_t SR;           
  volatile uint32_t MISR;         
       uint32_t RESERVED3;    
  volatile uint32_t SCR;          
} RTC_TypeDef;



 

typedef struct
{
  volatile uint32_t CR1;                      
  volatile uint32_t CR2;                      
       uint32_t RESERVED0;                
  volatile uint32_t FLTCR;                    
       uint32_t RESERVED1[6];             
       uint32_t RESERVED2;                
  volatile uint32_t IER;                      
  volatile uint32_t SR;                       
  volatile uint32_t MISR;                     
       uint32_t RESERVED3;                
  volatile uint32_t SCR;                      
       uint32_t RESERVED4[48];            
  volatile uint32_t BKP0R;                    
  volatile uint32_t BKP1R;                    
  volatile uint32_t BKP2R;                    
  volatile uint32_t BKP3R;                    
  volatile uint32_t BKP4R;                    
  volatile uint32_t BKP5R;                    
  volatile uint32_t BKP6R;                    
  volatile uint32_t BKP7R;                    
  volatile uint32_t BKP8R;                    
  volatile uint32_t BKP9R;                    
  volatile uint32_t BKP10R;                   
  volatile uint32_t BKP11R;                   
  volatile uint32_t BKP12R;                   
  volatile uint32_t BKP13R;                   
  volatile uint32_t BKP14R;                   
  volatile uint32_t BKP15R;                   
  volatile uint32_t BKP16R;                   
  volatile uint32_t BKP17R;                   
  volatile uint32_t BKP18R;                   
  volatile uint32_t BKP19R;                   
  volatile uint32_t BKP20R;                   
  volatile uint32_t BKP21R;                   
  volatile uint32_t BKP22R;                   
  volatile uint32_t BKP23R;                   
  volatile uint32_t BKP24R;                   
  volatile uint32_t BKP25R;                   
  volatile uint32_t BKP26R;                   
  volatile uint32_t BKP27R;                   
  volatile uint32_t BKP28R;                   
  volatile uint32_t BKP29R;                   
  volatile uint32_t BKP30R;                   
  volatile uint32_t BKP31R;                   
} TAMP_TypeDef;



 

typedef struct
{
  volatile uint32_t GCR;           
  uint32_t      RESERVED[16];  
  volatile uint32_t PDMCR;         
  volatile uint32_t PDMDLY;        
} SAI_TypeDef;

typedef struct
{
  volatile uint32_t CR1;          
  volatile uint32_t CR2;          
  volatile uint32_t FRCR;         
  volatile uint32_t SLOTR;        
  volatile uint32_t IMR;          
  volatile uint32_t SR;           
  volatile uint32_t CLRFR;        
  volatile uint32_t DR;           
} SAI_Block_TypeDef;



 

typedef struct
{
  volatile uint32_t CR1;          
  volatile uint32_t CR2;          
  volatile uint32_t SR;           
  volatile uint32_t DR;           
  volatile uint32_t CRCPR;        
  volatile uint32_t RXCRCR;       
  volatile uint32_t TXCRCR;       
  volatile uint32_t I2SCFGR;      
  volatile uint32_t I2SPR;        
} SPI_TypeDef;



 

typedef struct
{
  volatile uint32_t MEMRMP;       
  volatile uint32_t CFGR1;        
  volatile uint32_t EXTICR[4];    
  volatile uint32_t SCSR;         
  volatile uint32_t CFGR2;        
  volatile uint32_t SWPR;         
  volatile uint32_t SKR;          
} SYSCFG_TypeDef;



 

typedef struct
{
  volatile uint32_t CR1;          
  volatile uint32_t CR2;          
  volatile uint32_t SMCR;         
  volatile uint32_t DIER;         
  volatile uint32_t SR;           
  volatile uint32_t EGR;          
  volatile uint32_t CCMR1;        
  volatile uint32_t CCMR2;        
  volatile uint32_t CCER;         
  volatile uint32_t CNT;          
  volatile uint32_t PSC;          
  volatile uint32_t ARR;          
  volatile uint32_t RCR;          
  volatile uint32_t CCR1;         
  volatile uint32_t CCR2;         
  volatile uint32_t CCR3;         
  volatile uint32_t CCR4;         
  volatile uint32_t BDTR;         
  volatile uint32_t CCR5;         
  volatile uint32_t CCR6;         
  volatile uint32_t CCMR3;        
  volatile uint32_t DTR2;         
  volatile uint32_t ECR;          
  volatile uint32_t TISEL;        
  volatile uint32_t AF1;          
  volatile uint32_t AF2;          
  volatile uint32_t OR ;          
       uint32_t RESERVED0[220]; 
  volatile uint32_t DCR;          
  volatile uint32_t DMAR;         
} TIM_TypeDef;



 
typedef struct
{
  volatile uint32_t CR1;          
  volatile uint32_t CR2;          
  volatile uint32_t CR3;          
  volatile uint32_t BRR;          
  volatile uint32_t GTPR;         
  volatile uint32_t RTOR;         
  volatile uint32_t RQR;          
  volatile uint32_t ISR;          
  volatile uint32_t ICR;          
  volatile uint32_t RDR;          
  volatile uint32_t TDR;          
  volatile uint32_t PRESC;        
} USART_TypeDef;



 

typedef struct
{
  volatile uint16_t EP0R;             
  volatile uint16_t RESERVED0;        
  volatile uint16_t EP1R;             
  volatile uint16_t RESERVED1;        
  volatile uint16_t EP2R;             
  volatile uint16_t RESERVED2;        
  volatile uint16_t EP3R;             
  volatile uint16_t RESERVED3;        
  volatile uint16_t EP4R;             
  volatile uint16_t RESERVED4;        
  volatile uint16_t EP5R;             
  volatile uint16_t RESERVED5;        
  volatile uint16_t EP6R;             
  volatile uint16_t RESERVED6;        
  volatile uint16_t EP7R;             
  volatile uint16_t RESERVED7[17];    
  volatile uint16_t CNTR;             
  volatile uint16_t RESERVED8;        
  volatile uint16_t ISTR;             
  volatile uint16_t RESERVED9;        
  volatile uint16_t FNR;              
  volatile uint16_t RESERVEDA;        
  volatile uint16_t DADDR;            
  volatile uint16_t RESERVEDB;        
  volatile uint16_t BTABLE;           
  volatile uint16_t RESERVEDC;        
  volatile uint16_t LPMCSR;           
  volatile uint16_t RESERVEDD;        
  volatile uint16_t BCDR;             
  volatile uint16_t RESERVEDE;        
} USB_TypeDef;



 

typedef struct
{
  volatile uint32_t CSR;          
  volatile uint32_t CCR;          
} VREFBUF_TypeDef;



 

typedef struct
{
  volatile uint32_t CR;           
  volatile uint32_t CFR;          
  volatile uint32_t SR;           
} WWDG_TypeDef;




 
typedef struct
{
  volatile uint32_t CR;   
  volatile uint32_t SR;   
  volatile uint32_t DR;   
} RNG_TypeDef;



 

typedef struct
{
  volatile uint32_t CSR;           
  volatile uint32_t WDATA;         
  volatile uint32_t RDATA;         
} CORDIC_TypeDef;



 

typedef struct
{
  volatile uint32_t CFG1;           
  volatile uint32_t CFG2;           
  volatile uint32_t RESERVED0;      
  volatile uint32_t CR;             
  volatile uint32_t IMR;            
  volatile uint32_t SR;             
  volatile uint32_t ICR;            
  volatile uint32_t TX_ORDSET;      
  volatile uint32_t TX_PAYSZ;       
  volatile uint32_t TXDR;           
  volatile uint32_t RX_ORDSET;      
  volatile uint32_t RX_PAYSZ;       
  volatile uint32_t RXDR;           
  volatile uint32_t RX_ORDEXT1;     
  volatile uint32_t RX_ORDEXT2;     
} UCPD_TypeDef;



 



 
typedef struct
{
  volatile uint32_t MCR;             
  volatile uint32_t MISR;            
  volatile uint32_t MICR;            
  volatile uint32_t MDIER;           
  volatile uint32_t MCNTR;           
  volatile uint32_t MPER;            
  volatile uint32_t MREP;            
  volatile uint32_t MCMP1R;          
  uint32_t      RESERVED0;      
  volatile uint32_t MCMP2R;          
  volatile uint32_t MCMP3R;          
  volatile uint32_t MCMP4R;          
  uint32_t      RESERVED1[20];   
}HRTIM_Master_TypeDef;

 
typedef struct
{
  volatile uint32_t TIMxCR;      
  volatile uint32_t TIMxISR;     
  volatile uint32_t TIMxICR;     
  volatile uint32_t TIMxDIER;    
  volatile uint32_t CNTxR;       
  volatile uint32_t PERxR;       
  volatile uint32_t REPxR;       
  volatile uint32_t CMP1xR;      
  volatile uint32_t CMP1CxR;     
  volatile uint32_t CMP2xR;      
  volatile uint32_t CMP3xR;      
  volatile uint32_t CMP4xR;      
  volatile uint32_t CPT1xR;      
  volatile uint32_t CPT2xR;      
  volatile uint32_t DTxR;        
  volatile uint32_t SETx1R;      
  volatile uint32_t RSTx1R;      
  volatile uint32_t SETx2R;      
  volatile uint32_t RSTx2R;      
  volatile uint32_t EEFxR1;      
  volatile uint32_t EEFxR2;      
  volatile uint32_t RSTxR;       
  volatile uint32_t CHPxR;       
  volatile uint32_t CPT1xCR;     
  volatile uint32_t CPT2xCR;     
  volatile uint32_t OUTxR;       
  volatile uint32_t FLTxR;       
  volatile uint32_t TIMxCR2;     
  volatile uint32_t EEFxR3;      
  uint32_t   RESERVED0[3];   
}HRTIM_Timerx_TypeDef;

 
typedef struct
{
  volatile uint32_t CR1;         
  volatile uint32_t CR2;         
  volatile uint32_t ISR;         
  volatile uint32_t ICR;         
  volatile uint32_t IER;         
  volatile uint32_t OENR;        
  volatile uint32_t ODISR;       
  volatile uint32_t ODSR;        
  volatile uint32_t BMCR;        
  volatile uint32_t BMTRGR;      
  volatile uint32_t BMCMPR;      
  volatile uint32_t BMPER;       
  volatile uint32_t EECR1;       
  volatile uint32_t EECR2;       
  volatile uint32_t EECR3;       
  volatile uint32_t ADC1R;       
  volatile uint32_t ADC2R;       
  volatile uint32_t ADC3R;       
  volatile uint32_t ADC4R;       
  volatile uint32_t DLLCR;       
  volatile uint32_t FLTINR1;     
  volatile uint32_t FLTINR2;     
  volatile uint32_t BDMUPR;      
  volatile uint32_t BDTAUPR;     
  volatile uint32_t BDTBUPR;     
  volatile uint32_t BDTCUPR;     
  volatile uint32_t BDTDUPR;     
  volatile uint32_t BDTEUPR;     
  volatile uint32_t BDMADR;      
  volatile uint32_t BDTFUPR;     
  volatile uint32_t ADCER;       
  volatile uint32_t ADCUR;       
  volatile uint32_t ADCPS1;      
  volatile uint32_t ADCPS2;      
  volatile uint32_t FLTINR3;     
  volatile uint32_t FLTINR4;     
}HRTIM_Common_TypeDef;

 
typedef struct {
  HRTIM_Master_TypeDef sMasterRegs;
  HRTIM_Timerx_TypeDef sTimerxRegs[6];
  HRTIM_Common_TypeDef sCommonRegs;
}HRTIM_TypeDef;



 



 

#line 1140 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1147 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"
 







 





#line 1167 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 1201 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 1219 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1241 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 1251 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1260 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1269 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1290 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"




 
#line 1302 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1310 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"







 




 







 



 
#line 1365 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1375 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1383 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1413 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1434 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1443 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1452 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1469 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"



















 



 

  

 


  

 



 

 
 
 

 
 
 
 
 



 


 
#line 1556 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 1591 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 1623 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 1631 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"







#line 1646 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"







#line 1668 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1675 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1694 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1703 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"





 
#line 1715 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1722 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1730 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1737 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"





#line 1751 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 1759 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1766 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1773 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1780 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1787 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1794 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1801 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1808 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1815 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1822 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"





 
#line 1834 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1841 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1848 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1855 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1862 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1869 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1876 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1883 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1890 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 




#line 1902 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"





 








 








 
#line 1933 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1942 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1951 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1960 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1969 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 1979 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1988 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 1997 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 2006 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 2015 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 2025 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 2034 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 2043 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 2052 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 2061 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 2071 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 2080 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 




 






#line 2101 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"







#line 2116 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 2125 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 2134 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 2143 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 




#line 2155 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 2164 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"





 




#line 2180 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 2189 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"





 




#line 2205 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 2214 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"





 




#line 2230 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 2239 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"





 




 




 




 




 
#line 2287 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 2311 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 2335 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 2347 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 2358 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 




 
 
#line 2399 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 2433 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 2443 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 2451 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

















#line 2475 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 2485 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 









 
 
 
 
 
 




#line 2513 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"









#line 2528 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 2535 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

















 
 
 
 
 
 
#line 2602 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 




 




 
 
 
 
 
 




 




 
#line 2645 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 




 




 
 
 
 

 
#line 2686 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 2694 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 2701 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"











 
#line 2740 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
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#line 14923 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"





#line 14936 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"





#line 14948 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"







#line 14961 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"









 
#line 15028 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 15090 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 15119 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"


 






#line 15134 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 15142 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"











#line 15159 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 15167 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"





 






#line 15186 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"







#line 15200 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 






#line 15214 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 15222 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"











#line 15239 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 15247 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"





 






#line 15266 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"







#line 15280 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 15288 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 15296 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"





#line 15307 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 15315 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"





 
#line 15381 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 15389 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 




 




 




 




 




 




 




 
#line 15438 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 




 
#line 15456 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"







#line 15481 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 15488 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 15495 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 15502 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 15509 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 15519 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 15528 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 15576 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 15623 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 




 
#line 15637 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 15645 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 15653 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 15661 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 15674 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 15681 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 




















#line 15714 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 15721 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 




 
 
 
 
 
 
#line 15754 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 15777 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 15800 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 






















#line 15830 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 15838 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"







#line 15863 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 15880 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 




 




 




 
#line 15903 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 15910 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"
 
 
 
 
 
 
#line 16007 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 16073 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 16158 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 16166 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 16174 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 16182 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 16199 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 16291 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 16338 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 




 




 
#line 16357 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
 
 
 
 
 
#line 16378 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 




 
 
 
 
 
#line 16397 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 16409 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 

                                                                          
#line 16419 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"


                                                                          
#line 16429 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"
                                                                          
#line 16437 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
 
 
 
 
#line 16450 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 16467 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 16480 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 16490 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 






 
#line 16507 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"



 


 
#line 16523 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 





 
 




 




 




 




 




 




 




 




 

 




 




 




 




 




 




 




 




 

 


 


 


 


 


 


 


 


 


 


 


 


 


 


 


 


 

 




 




 




 




 




 




 




 




 

 




#line 16720 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"





 




#line 16738 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"





 




#line 16756 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"





 




#line 16774 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"





 




#line 16792 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"





 




#line 16810 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"





 




#line 16828 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"





 




#line 16846 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"





 

 


#line 16862 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"



 


#line 16874 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"



 


#line 16886 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"



 


#line 16898 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"



 


#line 16910 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"



 


#line 16922 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"



 


#line 16934 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"



 


#line 16946 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"



 


#line 16958 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"



 


#line 16970 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"



 


#line 16982 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"



 


#line 16994 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"



 


#line 17006 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"



 


#line 17018 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"



 


#line 17030 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"



 


#line 17042 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"



 
 
 
 
 
 
#line 17103 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 17117 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 17167 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 17214 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 17274 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 17315 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 




 




 




 
#line 17344 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 




 




 




 




 
 
 
 
 
 
#line 17381 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"





 
#line 17397 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

#line 17404 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"





 






 



 



 

 













 





 
#line 17454 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 


 


 






 
#line 17485 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"






 


 
#line 17502 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 


 


 





 


 
#line 17525 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 


 


 


 




 





 


 





 



 


 


 


 
#line 17581 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 




 
#line 17594 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 17602 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 




 
#line 17619 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 17629 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 17638 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 17647 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 




 




 
#line 17665 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 17679 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 17691 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 17703 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 17763 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 17792 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 17804 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 17813 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 17822 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 17832 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 17842 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 




 
#line 17855 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 17864 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 17873 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 17883 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 17892 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 17901 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 17913 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 17923 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 17935 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 17945 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 17954 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 17962 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 




 
#line 17977 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 17989 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 




 



 


 




 






 
#line 18021 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 




 






 
#line 18041 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 18049 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 
#line 18057 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 






 
#line 18072 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h"

 






 




 


 


 


 


 




 


 
 
 
 
 
 
 

 

 









 

  

 

#line 118 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h"
#line 129 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h"



 



 
typedef enum
{
  RESET = 0,
  SET = !RESET
} FlagStatus, ITStatus;

typedef enum
{
  DISABLE = 0,
  ENABLE = !DISABLE
} FunctionalState;


typedef enum
{
  SUCCESS = 0,
  ERROR = !SUCCESS
} ErrorStatus;



 




 
















 
 
#line 189 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h"

 
#line 198 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h"

 
#line 207 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h"

 
#line 216 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h"

 
#line 225 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h"

 
#line 234 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h"




 

#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h"

















 

 
#line 624 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h"

#line 242 "../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h"









 



 




#line 30 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

















 

 







 
 
 



 
#line 48 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"


 



 
#line 95 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 103 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"






 



 





 



 
#line 141 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 208 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"


 



 
#line 221 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"


 



 




 



 






 



 

#line 258 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"






#line 270 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"








 



 
#line 297 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"





#line 341 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 351 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 413 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"


 



 

#line 518 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"



 



 

#line 535 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"



 



 

#line 554 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"









 




 
#line 580 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"


 



 





 



 


















#line 630 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"





#line 641 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 648 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"














 



 





 



 
#line 686 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 695 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 706 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 818 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 835 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"


 



 
#line 858 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"


 



 





 



 






 



 















 
 







 



 
  


 






 








 



 














 



 










 



 







































 



 


#line 1026 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"






 



 

 
#line 1048 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

 












 



 




























#line 1104 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"



 




 















 




 
#line 1145 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"


 



 









#line 1175 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"



 



 



#line 1213 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 1223 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 1242 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"










#line 1269 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"



 



 




 



 

























 




 








 



 




 



 
#line 1349 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"



 



 

#line 1366 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 1378 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 1409 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"



 



 











 

#line 1457 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 1471 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"



 



 

 



 



 



 








 




 




 



 
#line 1522 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

 












#line 1559 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"


 



 
#line 1589 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"



 



 
#line 1604 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"



 



 








#line 1632 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 1643 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"


 



 

#line 1673 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 1681 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"






#line 1697 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"





 



 





 



 



 



 
#line 1737 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"


 



 



 



 






 




 



 

 



 





 



 
#line 1798 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"









 




 
#line 1826 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 1847 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 1858 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 1867 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 1880 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 1889 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"



 



 







 



 
#line 1925 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 1940 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"


#line 1973 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"



 



 
#line 2140 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"



#line 2150 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"


 

#line 2164 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"



 







 



 

#line 2187 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"



 



 

#line 2215 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"


 



 










 



 














 




 




 




 







 




 
#line 2293 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"



 




 
#line 2337 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 2351 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"


 




 








#line 2625 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 2639 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 2856 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 2870 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 2877 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 2898 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 3046 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

 



#line 3071 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 3092 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 3209 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 3218 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 3235 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 3250 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"






#line 3279 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

















#line 3305 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"





#line 3332 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"







#line 3347 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 3380 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 3398 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"












#line 3416 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 3437 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 3470 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"



 



 




 



 
#line 3493 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 3521 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 3536 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"






 



 













#line 3585 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 3611 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 3618 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 3630 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"


 



 

#line 3644 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"








 



 
#line 3665 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"


 



 







 



 













 




 









#line 3719 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"


 



 












#line 3745 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 3754 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"

#line 3763 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"








 



 








#line 3796 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"




 



 

#line 3813 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"






 



 




 



 
#line 3847 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"


 



 







 



 
#line 3874 "../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h"


 



 





 



 





 



 



 








#line 31 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
#line 1 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stddef.h"
 






 

 
 
 





 





#line 34 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stddef.h"




  typedef signed int ptrdiff_t;



  



    typedef unsigned int size_t;    
#line 57 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stddef.h"



   



      typedef unsigned short wchar_t;  
#line 82 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stddef.h"



    




   




  typedef long double max_align_t;









#line 114 "C:\\Keil_v5\\ARM\\ARMCC\\Bin\\..\\include\\stddef.h"



 

#line 32 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"

 



 
typedef enum
{
  HAL_OK       = 0x00U,
  HAL_ERROR    = 0x01U,
  HAL_BUSY     = 0x02U,
  HAL_TIMEOUT  = 0x03U
} HAL_StatusTypeDef;



 
typedef enum
{
  HAL_UNLOCKED = 0x00U,
  HAL_LOCKED   = 0x01U
} HAL_LockTypeDef;

 




























 


#line 102 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"







#line 124 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"


 
#line 153 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"



 









 


#line 185 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"



 



 


#line 202 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"








#line 28 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"



 



 

 


 



 
typedef struct
{
  uint32_t PLLState;   
 

  uint32_t PLLSource;  
 

  uint32_t PLLM;       
 

  uint32_t PLLN;       
 

  uint32_t PLLP;       
 

  uint32_t PLLQ;       
 

  uint32_t PLLR;       

 

}RCC_PLLInitTypeDef;



 
typedef struct
{
  uint32_t OscillatorType;       
 

  uint32_t HSEState;             
 

  uint32_t LSEState;             
 

  uint32_t HSIState;             
 

  uint32_t HSICalibrationValue;  
 

  uint32_t LSIState;             
 

  uint32_t HSI48State;             
 

  RCC_PLLInitTypeDef PLL;         

}RCC_OscInitTypeDef;



 
typedef struct
{
  uint32_t ClockType;             
 

  uint32_t SYSCLKSource;          
 

  uint32_t AHBCLKDivider;         
 

  uint32_t APB1CLKDivider;        
 

  uint32_t APB2CLKDivider;        
 

}RCC_ClkInitTypeDef;



 

 


 



 




 



 
#line 150 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"


 



 





 



 





 



 





 



 




 



 




 



 





 



 
#line 231 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"


 



 
#line 268 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"


 



 






 



 






 



 





 



 





 



 






 



 





 



 





 



 
#line 357 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"


 



 







 



 






 



 




 

#line 402 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

 




 



 
#line 421 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"


 



 







 



 
#line 448 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"


 










 
 




 



 
#line 480 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

 



 



 






 



 

 



 







 

#line 523 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 531 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 539 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 547 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 555 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 563 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 571 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

















 







 

#line 605 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 613 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 621 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 629 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 637 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 645 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 653 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 661 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 671 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 679 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 689 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 697 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 707 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 717 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 725 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"










































 







 

#line 786 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 796 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"











 







 

#line 824 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 832 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 840 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 850 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 858 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 866 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 874 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 882 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 890 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 898 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 906 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 914 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 922 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 932 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 942 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 950 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 958 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 966 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 976 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 984 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 992 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 1000 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 1008 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 1018 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 1026 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"































































 







 

#line 1106 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 1114 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 1122 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 1130 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 1138 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 1148 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 1156 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 1164 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 1172 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 1182 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 1190 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

#line 1200 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

































 







 































 







 
















































































 







 



















 







 





























































































































 







 
































































 




 



































 




 



















































































 




 






















 




 






















































































































 




 



































































 








 




































 








 
























































































 








 



















 








 
































































































































 








 
































































 








 




































 








 
























































































 








 



















 








 




























































































































 








 

































































 



 






 






 



 








 






 
















 











 











 












 


























 
#line 2856 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"




















 
#line 2894 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"







 



























 










 









 













 












 






































 
#line 3027 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"







 














 













 










 









 















 





















 






 













 














 















 














 






 




















 
#line 3224 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"



 



 

 


 
 







 




 

 


 

#line 3263 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"


























































#line 3329 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"












 

 
#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h"















 

 







 
#line 28 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h"



 



 

 



 



 
typedef struct
{
  uint32_t PeriphClockSelection;   
 

  uint32_t Usart1ClockSelection;   
 

  uint32_t Usart2ClockSelection;   
 

  uint32_t Usart3ClockSelection;   
 


  uint32_t Uart4ClockSelection;    
 



  uint32_t Uart5ClockSelection;    
 



  uint32_t Lpuart1ClockSelection;  
 

  uint32_t I2c1ClockSelection;     
 

  uint32_t I2c2ClockSelection;     
 

  uint32_t I2c3ClockSelection;     
 



  uint32_t I2c4ClockSelection;     
 


  uint32_t Lptim1ClockSelection;   
 

  uint32_t Sai1ClockSelection;     
 

  uint32_t I2sClockSelection;     
 


  uint32_t FdcanClockSelection;     
 



  uint32_t UsbClockSelection;      
 


  uint32_t RngClockSelection;      
 

  uint32_t Adc12ClockSelection;    
 


  uint32_t Adc345ClockSelection;   
 



  uint32_t QspiClockSelection;     
 


  uint32_t RTCClockSelection;      
 
}RCC_PeriphCLKInitTypeDef;



 
typedef struct
{
  uint32_t Prescaler;             
 

  uint32_t Source;                
 

  uint32_t Polarity;              
 

  uint32_t ReloadValue;           

 

  uint32_t ErrorLimitValue;       
 

  uint32_t HSI48CalibrationValue; 
 

}RCC_CRSInitTypeDef;



 
typedef struct
{
  uint32_t ReloadValue;           
 

  uint32_t HSI48CalibrationValue; 
 

  uint32_t FreqErrorCapture;      

 

  uint32_t FreqErrorDirection;    


 

}RCC_CRSSynchroInfoTypeDef;



 

 


 



 




 



 
#line 229 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h"


 




 






 



 






 



 






 




 






 





 






 




 






 



 





 



 





 



 





 



 






 



 






 



 






 



 





 




 




 



 




 



 





 




 





 





 





 





 





 




 



 



 
#line 460 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h"


 



 





 



 
#line 485 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h"


 



 




 



 




 



 



 



 





 



 




 



 
#line 544 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h"



 



 
#line 559 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h"



 



 

 


 










 









 











 









 











 









 












 









 














 









 













 









 










 








 











 








 










 








 












 








 













 









 













 










 













 










 













 









 












 







 













 







 











 








 










 








 












 








 







 




 





 





 





 






 






 






 





 





 









 









 





 





 












 











 










 












 
 


#line 1154 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h"













 















 

 


#line 1198 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h"




 



 




 





 






 





 











 




 



 

 


 



 

HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
void              HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
uint32_t          HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);



 



 

void              HAL_RCCEx_EnableLSECSS(void);
void              HAL_RCCEx_DisableLSECSS(void);
void              HAL_RCCEx_EnableLSECSS_IT(void);
void              HAL_RCCEx_LSECSS_IRQHandler(void);
void              HAL_RCCEx_LSECSS_Callback(void);
void              HAL_RCCEx_EnableLSCO(uint32_t LSCOSource);
void              HAL_RCCEx_DisableLSCO(void);



 



 

void              HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
void              HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
void              HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
uint32_t          HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
void              HAL_RCCEx_CRS_IRQHandler(void);
void              HAL_RCCEx_CRS_SyncOkCallback(void);
void              HAL_RCCEx_CRS_SyncWarnCallback(void);
void              HAL_RCCEx_CRS_ExpectedSyncCallback(void);
void              HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);



 



 

 


 






#line 1445 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h"



















#line 1471 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h"

#line 1478 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h"










































































#line 1558 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h"

































 



 



 







#line 3345 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"

 


 




 

 
HAL_StatusTypeDef HAL_RCC_DeInit(void);
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);



 



 

 
void              HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
void              HAL_RCC_EnableCSS(void);
void              HAL_RCC_EnableLSECSS(void);
void              HAL_RCC_DisableLSECSS(void);
uint32_t          HAL_RCC_GetSysClockFreq(void);
uint32_t          HAL_RCC_GetHCLKFreq(void);
uint32_t          HAL_RCC_GetPCLK1Freq(void);
uint32_t          HAL_RCC_GetPCLK2Freq(void);
void              HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
void              HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
 
void              HAL_RCC_NMI_IRQHandler(void);
 
void              HAL_RCC_CSSCallback(void);



 



 



 



 







#line 213 "../Core/Inc/stm32g4xx_hal_conf.h"


#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h"
















 

 







 
#line 29 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h"



 




 

 



 


 
typedef struct
{
  uint32_t Pin;        
 

  uint32_t Mode;       
 

  uint32_t Pull;       
 

  uint32_t Speed;      
 

  uint32_t Alternate;  
 
} GPIO_InitTypeDef;



 
typedef enum
{
  GPIO_PIN_RESET = 0U,
  GPIO_PIN_SET
} GPIO_PinState;


 

 


 


 
#line 101 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h"




 









  







    



 





 




 






 




 





 



 

 


 






 







 







 







 







 




 

 


 
#line 233 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h"


 



 





#line 257 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h"











 

 
#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h"
















 


 







 
#line 30 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h"



 




 

 
 


 



 



 







 
#line 71 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h"



 
#line 97 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h"



 
#line 119 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h"



 
#line 134 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h"



 
#line 151 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h"



 
#line 170 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h"



 
#line 186 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h"



 
#line 212 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h"



 
#line 226 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h"



 
#line 240 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h"



 
#line 252 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h"



 
#line 267 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h"



 







 
#line 287 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h"



 






 



 

 


 



 
#line 317 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h"



 



 

 


 



 







#line 272 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h"

 



 




 

 
void              HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
void              HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);



 




 

 
GPIO_PinState     HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void              HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
void              HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void              HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
void              HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);



 



 



 



 







#line 217 "../Core/Inc/stm32g4xx_hal_conf.h"


#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"
















 

 







 
#line 29 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"



 



 

 


 



 
typedef struct
{
  uint32_t Request;                   
 

  uint32_t Direction;                 

 

  uint32_t PeriphInc;                 
 

  uint32_t MemInc;                    
 

  uint32_t PeriphDataAlignment;       
 

  uint32_t MemDataAlignment;          
 

  uint32_t Mode;                      


 

  uint32_t Priority;                  
 
} DMA_InitTypeDef;



 
typedef enum
{
  HAL_DMA_STATE_RESET             = 0x00U,   
  HAL_DMA_STATE_READY             = 0x01U,   
  HAL_DMA_STATE_BUSY              = 0x02U,   
  HAL_DMA_STATE_TIMEOUT           = 0x03U,   
} HAL_DMA_StateTypeDef;



 
typedef enum
{
  HAL_DMA_FULL_TRANSFER      = 0x00U,     
  HAL_DMA_HALF_TRANSFER      = 0x01U      
} HAL_DMA_LevelCompleteTypeDef;




 
typedef enum
{
  HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,     
  HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,     
  HAL_DMA_XFER_ERROR_CB_ID         = 0x02U,     
  HAL_DMA_XFER_ABORT_CB_ID         = 0x03U,     
  HAL_DMA_XFER_ALL_CB_ID           = 0x04U      

} HAL_DMA_CallbackIDTypeDef;



 
typedef struct __DMA_HandleTypeDef
{
  DMA_Channel_TypeDef    *Instance;                                                   

  DMA_InitTypeDef       Init;                                                         

  HAL_LockTypeDef       Lock;                                                         

  volatile HAL_DMA_StateTypeDef  State;                                                   

  void                  *Parent;                                                      

  void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma);                        

  void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma);                    

  void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma);                       

  void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma);                       

  volatile uint32_t          ErrorCode;                                                   

  DMA_TypeDef            *DmaBaseAddress;                                             

  uint32_t               ChannelIndex;                                                

  DMAMUX_Channel_TypeDef           *DMAmuxChannel;                                    

  DMAMUX_ChannelStatus_TypeDef     *DMAmuxChannelStatus;                              

  uint32_t                         DMAmuxChannelStatusMask;                           

  DMAMUX_RequestGen_TypeDef        *DMAmuxRequestGen;                                 

  DMAMUX_RequestGenStatus_TypeDef  *DMAmuxRequestGenStatus;                           

  uint32_t                         DMAmuxRequestGenStatusMask;                        

} DMA_HandleTypeDef;


 

 



 



 
#line 172 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"


 



 















#line 200 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"

#line 211 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"

#line 218 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"

#line 225 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"




#line 239 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"









#line 255 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"

#line 263 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"







#line 276 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"







#line 291 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"











#line 309 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"









#line 327 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"

#line 334 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"




















 



 





 



 




 



 




 



 





 



 





 



 




 



 






 




 





 



 
#line 474 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"


 



 

 


 




 






 






 



 





 

#line 547 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"





 
#line 584 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"





 
#line 621 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"





 
#line 658 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"












 
#line 678 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"












 
#line 698 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"










 











 











 






 




 

 
#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h"
















 

 







 
#line 29 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h"



 



 

 


 



 




 
typedef struct
{
  uint32_t SyncSignalID;  
 

  uint32_t SyncPolarity;  
 

  FunctionalState SyncEnable;  
 


  FunctionalState EventEnable;    
 

  uint32_t RequestNumber; 
 


} HAL_DMA_MuxSyncConfigTypeDef;




 
typedef struct
{
  uint32_t SignalID;      
 

  uint32_t Polarity;       
 

  uint32_t RequestNumber;  
 

} HAL_DMA_MuxRequestGeneratorConfigTypeDef;



 

 


 



 
#line 122 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h"



 



 







 



 
#line 163 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h"



 



 







 



 

 

 


 

 


 

 
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma,
                                                      HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
 

 
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
 

void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);



 



 

 



 


























 




 



 







#line 748 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"

 



 



 
 
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);


 



 
 
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress,
                                   uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel,
                                          uint32_t Timeout);
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);



 



 
 
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);


 



 

 


 

































 

 



 



 







#line 221 "../Core/Inc/stm32g4xx_hal_conf.h"


#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h"
















 
 







 
#line 28 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h"



 




 

 


 





 
typedef struct
{
  uint8_t                Enable;                
 
  uint8_t                Number;                
 
  uint32_t               BaseAddress;            
  uint8_t                Size;                  
 
  uint8_t                SubRegionDisable;      
 
  uint8_t                TypeExtField;          
 
  uint8_t                AccessPermission;      
 
  uint8_t                DisableExec;           
 
  uint8_t                IsShareable;           
 
  uint8_t                IsCacheable;           
 
  uint8_t                IsBufferable;          
 
}MPU_Region_InitTypeDef;


 




 

 



 



 
#line 100 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h"


 



 





 




 






 



 




 



 




 



 




 



 




 



 




 



 






 



 
#line 213 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h"


 



 
#line 226 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h"


 



 
#line 241 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h"


 




 

 


 



 

 


 




 
 
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
void HAL_NVIC_SystemReset(void);
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);



 




 
 
uint32_t HAL_NVIC_GetPriorityGrouping(void);
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
void HAL_SYSTICK_IRQHandler(void);
void HAL_SYSTICK_Callback(void);


void HAL_MPU_Enable(uint32_t MPU_Control);
void HAL_MPU_Disable(void);
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);



 



 

  
 
 
 


 




































#line 357 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h"

#line 366 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h"

#line 395 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h"






 

 



 



 








#line 225 "../Core/Inc/stm32g4xx_hal_conf.h"


























#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h"
















 

 







 
#line 29 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h"



 




 

 



 
typedef enum
{
  HAL_EXTI_COMMON_CB_ID         = 0x00UL
} EXTI_CallbackIDTypeDef;




 
typedef struct
{
  uint32_t Line;                     
  void (* PendingCallback)(void);    
} EXTI_HandleTypeDef;



 
typedef struct
{
  uint32_t Line;      
 
  uint32_t Mode;      
 
  uint32_t Trigger;   
 
  uint32_t GPIOSel;   

 
} EXTI_ConfigTypeDef;



 

 


 



 
#line 131 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h"


 



 





 



 






 




 
#line 167 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h"


 



 

 


 



 

 


 


 
#line 197 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h"



 








 




 




 




 

 


 
#line 236 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h"








#line 251 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h"










 


 



 




 
 
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);


 




 
 
void              HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
uint32_t          HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
void              HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
void              HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);



 



 



 



 







#line 253 "../Core/Inc/stm32g4xx_hal_conf.h"


#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h"
















 

 







 
#line 29 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h"





 



 

 


 



 
typedef enum
{
  HAL_FDCAN_STATE_RESET      = 0x00U,  
  HAL_FDCAN_STATE_READY      = 0x01U,  
  HAL_FDCAN_STATE_BUSY       = 0x02U,  
  HAL_FDCAN_STATE_ERROR      = 0x03U   
} HAL_FDCAN_StateTypeDef;



 
typedef struct
{
  uint32_t ClockDivider;                 



 

  uint32_t FrameFormat;                  
 

  uint32_t Mode;                         
 

  FunctionalState AutoRetransmission;    
 

  FunctionalState TransmitPause;         
 

  FunctionalState ProtocolException;      
 

  uint32_t NominalPrescaler;             

 

  uint32_t NominalSyncJumpWidth;         


 

  uint32_t NominalTimeSeg1;              
 

  uint32_t NominalTimeSeg2;              
 

  uint32_t DataPrescaler;                

 

  uint32_t DataSyncJumpWidth;            


 

  uint32_t DataTimeSeg1;                 
 

  uint32_t DataTimeSeg2;                 
 

  uint32_t StdFiltersNbr;                
 

  uint32_t ExtFiltersNbr;                
 

  uint32_t TxFifoQueueMode;              
 

} FDCAN_InitTypeDef;



 
typedef struct
{
  uint32_t IdType;           
 

  uint32_t FilterIndex;      


 

  uint32_t FilterType;       


 

  uint32_t FilterConfig;     
 

  uint32_t FilterID1;        


 

  uint32_t FilterID2;        


 

} FDCAN_FilterTypeDef;



 
typedef struct
{
  uint32_t Identifier;          


 

  uint32_t IdType;              

 

  uint32_t TxFrameType;         
 

  uint32_t DataLength;          
 

  uint32_t ErrorStateIndicator; 
 

  uint32_t BitRateSwitch;       

 

  uint32_t FDFormat;            

 

  uint32_t TxEventFifoControl;  
 

  uint32_t MessageMarker;       

 

} FDCAN_TxHeaderTypeDef;



 
typedef struct
{
  uint32_t Identifier;            


 

  uint32_t IdType;                
 

  uint32_t RxFrameType;           
 

  uint32_t DataLength;            
 

  uint32_t ErrorStateIndicator;   
 

  uint32_t BitRateSwitch;         

 

  uint32_t FDFormat;              

 

  uint32_t RxTimestamp;           

 

  uint32_t FilterIndex;           


 

  uint32_t IsFilterMatchingFrame; 


 

} FDCAN_RxHeaderTypeDef;



 
typedef struct
{
  uint32_t Identifier;          


 

  uint32_t IdType;              
 

  uint32_t TxFrameType;         
 

  uint32_t DataLength;          
 

  uint32_t ErrorStateIndicator; 
 

  uint32_t BitRateSwitch;       

 

  uint32_t FDFormat;            

 

  uint32_t TxTimestamp;         

 

  uint32_t MessageMarker;       

 

  uint32_t EventType;           
 

} FDCAN_TxEventFifoTypeDef;



 
typedef struct
{
  uint32_t FilterList;     


 

  uint32_t FilterIndex;    


 

  uint32_t MessageStorage; 
 

  uint32_t MessageIndex;   




 

} FDCAN_HpMsgStatusTypeDef;



 
typedef struct
{
  uint32_t LastErrorCode;     
 

  uint32_t DataLastErrorCode; 

 

  uint32_t Activity;          
 

  uint32_t ErrorPassive;      


 

  uint32_t Warning;           



 

  uint32_t BusOff;            


 

  uint32_t RxESIflag;         


 

  uint32_t RxBRSflag;         


 

  uint32_t RxFDFflag;         


 

  uint32_t ProtocolException; 


 

  uint32_t TDCvalue;          
 

} FDCAN_ProtocolStatusTypeDef;



 
typedef struct
{
  uint32_t TxErrorCnt;     
 

  uint32_t RxErrorCnt;     
 

  uint32_t RxErrorPassive; 



 

  uint32_t ErrorLogging;   



 

} FDCAN_ErrorCountersTypeDef;



 
typedef struct
{
  uint32_t StandardFilterSA; 
 

  uint32_t ExtendedFilterSA; 
 

  uint32_t RxFIFO0SA;        
 

  uint32_t RxFIFO1SA;        
 

  uint32_t TxEventFIFOSA;    
 

  uint32_t TxFIFOQSA;        
 

} FDCAN_MsgRamAddressTypeDef;



 



typedef struct

{
  FDCAN_GlobalTypeDef         *Instance;         

  FDCAN_InitTypeDef           Init;              

  FDCAN_MsgRamAddressTypeDef  msgRam;            

  uint32_t                    LatestTxFifoQRequest; 
 

  volatile HAL_FDCAN_StateTypeDef State;             

  HAL_LockTypeDef             Lock;              

  volatile uint32_t               ErrorCode;         

#line 459 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h"

} FDCAN_HandleTypeDef;

#line 491 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h"



 

 


 



 
#line 520 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h"






 



 





 



 







 



 
#line 569 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h"


 



 




 



 




 



 




 



 
#line 619 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h"


 



 




 



 




 



 




 



 




 



 






 



 
#line 680 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h"


 



 





 



 




 



 




 



 






 



 
#line 734 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h"


 



 






 



 




 



 





 



 




 



 




 



 




 



 
#line 814 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h"


 



 






 



 




 



 
#line 865 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h"


 



 



 





 



 



 



 




 



 





 



 





 



 





 



 
#line 939 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h"


 



 





 



 



 
#line 984 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h"


 



 
#line 1022 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h"


 



 

 


 




 
#line 1048 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h"







 









 









 








 









 








 








 




 

 


 



 
 
HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan);
void              HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan);
void              HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan);

#line 1159 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h"


 



 
 
HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig);
HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd,
                                               uint32_t NonMatchingExt, uint32_t RejectRemoteStd,
                                               uint32_t RejectRemoteExt);
HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask);
HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode);
HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue);
HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler);
HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation);
HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
uint16_t          HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation,
                                                 uint32_t TimeoutPeriod);
HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
uint16_t          HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset,
                                                      uint32_t TdcFilter);
HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);


 



 
 
HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader,
                                                uint8_t *pTxData);
uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation,
                                         FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData);
HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent);
HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan,
                                                         FDCAN_HpMsgStatusTypeDef *HpMsgStatus);
HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus);
HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters);
uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex);
uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo);
uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan);
uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);


 



 
 
HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine);
HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs,
                                                 uint32_t BufferIndexes);
HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs);
void              HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan);


 



 
 
void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);
void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);
void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);
void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan);
void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan);
void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan);
void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan);
void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan);
void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);


 



 
 
uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan);
HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);


 



 

 
 


 



 

 


 



 

 


 
#line 1409 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h"


 

 
 



 



 






#line 257 "../Core/Inc/stm32g4xx_hal_conf.h"


#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h"















 

 







 
#line 28 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h"



 



 

 


 



 
typedef struct
{
  uint32_t TypeErase;   
 
  uint32_t Banks;       

 
  uint32_t Page;        

 
  uint32_t NbPages;     
 
} FLASH_EraseInitTypeDef;



 
typedef struct
{
  uint32_t OptionType;     
 
  uint32_t WRPArea;        

 
  uint32_t WRPStartOffset; 
 
  uint32_t WRPEndOffset;   
 
  uint32_t RDPLevel;       
 
  uint32_t USERType;       
 
  uint32_t USERConfig;     







 
  uint32_t PCROPConfig;    

 
  uint32_t PCROPStartAddr; 

 
  uint32_t PCROPEndAddr;   
 
  uint32_t BootEntryPoint; 
 
  uint32_t SecBank;        




 
  uint32_t SecSize;        


 
} FLASH_OBProgramInitTypeDef;



 
typedef enum
{
  FLASH_PROC_NONE = 0,
  FLASH_PROC_PAGE_ERASE,
  FLASH_PROC_MASS_ERASE,
  FLASH_PROC_PROGRAM,
  FLASH_PROC_PROGRAM_LAST
} FLASH_ProcedureTypeDef;



 
typedef enum
{
  FLASH_CACHE_DISABLED = 0,
  FLASH_CACHE_ICACHE_ENABLED,
  FLASH_CACHE_DCACHE_ENABLED,
  FLASH_CACHE_ICACHE_DCACHE_ENABLED
} FLASH_CacheTypeDef;



 
typedef struct
{
  HAL_LockTypeDef             Lock;               
  volatile uint32_t               ErrorCode;          
  volatile FLASH_ProcedureTypeDef ProcedureOnGoing;   
  volatile uint32_t               Address;            
  volatile uint32_t               Bank;               
  volatile uint32_t               Page;               
  volatile uint32_t               NbPagesToErase;     
  volatile FLASH_CacheTypeDef     CacheToReactivate;  
} FLASH_ProcessTypeDef;



 

 


 



 
#line 175 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h"


 



 




 



 
#line 198 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h"


 




 







 



 
#line 224 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h"


 



 
#line 237 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h"


 



 




 



 






 



 
#line 286 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h"


 



 







 



 




 



 




 



 




 



 




 



 




 



 




 



 




 




 




 



 




 


#line 395 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h"



 




 



 




 



 




 



 




 



 




 



 





 



 




 



 






 



 
#line 490 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h"


 



 













 



 
#line 533 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h"

#line 544 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h"


 




 






 



 

 



 






















 






















 





 





 





 





 





 





 






 








 








 









 








 





 




 




 










 













 


























 



























 





 

 
#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h"















 

 







 
#line 28 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h"



 



 

 

 

 

 


 

 


 
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
HAL_StatusTypeDef HAL_FLASHEx_EnableSecMemProtection(uint32_t Bank);
void              HAL_FLASHEx_EnableDebugger(void);
void              HAL_FLASHEx_DisableDebugger(void);


 



 



 
void              FLASH_PageErase(uint32_t Page, uint32_t Banks);
void              FLASH_FlushCaches(void);


 



 



 







#line 800 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h"
#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h"















 

 







 
#line 28 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h"



 



 

 
 
 


 



 
 
 HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void);
 HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void);

 HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig);



 



 



 



 







#line 801 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h"

 


 
extern FLASH_ProcessTypeDef pFlash;


 

 


 

 


 
HAL_StatusTypeDef  HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
HAL_StatusTypeDef  HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
 
void               HAL_FLASH_IRQHandler(void);
 
void               HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
void               HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);


 

 


 
HAL_StatusTypeDef  HAL_FLASH_Unlock(void);
HAL_StatusTypeDef  HAL_FLASH_Lock(void);
 
HAL_StatusTypeDef  HAL_FLASH_OB_Unlock(void);
HAL_StatusTypeDef  HAL_FLASH_OB_Lock(void);
HAL_StatusTypeDef  HAL_FLASH_OB_Launch(void);


 

 


 
uint32_t HAL_FLASH_GetError(void);


 



 



 
HAL_StatusTypeDef  FLASH_WaitForLastOperation(uint32_t Timeout);


 

 


 


#line 885 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h"







 

 


 









#line 914 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h"
















#line 936 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h"
























































#line 1000 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h"


 



 



 







#line 261 "../Core/Inc/stm32g4xx_hal_conf.h"














































#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h"
















 

 







 
#line 29 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h"



 



 

 



 



 
typedef struct
{
  uint32_t PVDLevel;   
 

  uint32_t Mode;      
 
}PWR_PVDTypeDef;




 

 



 




 
#line 79 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h"


 



 
#line 93 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h"


 






 




 



 




 



 




 




 



 



 



 



 

 


 








































 





















 






 





 





 





 





 





 





 






 






 









 









 





 





 




 


 


 






#line 328 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h"










 

 
#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h"
















 

 







 
#line 29 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h"



 



 


 



 




 
typedef struct
{
  uint32_t PVMType;   
 
  uint32_t Mode;      
 
}PWR_PVMTypeDef;



 

 



 



 



 




 
#line 94 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h"


 



 
#line 109 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h"


 



 
#line 123 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h"


 





 







 




 




 



 




 



 
#line 179 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h"


 



 
#line 193 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h"


 



 
#line 208 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h"


 



 
#line 223 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h"


 










 
#line 245 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h"

#line 258 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h"


 



 

 


 





 





 





 





 





 





 





 






 






 









 









 





 





 









 





 





 





 





 





 





 






 






 









 









 





 





 








 





 





 





 





 





 





 






 






 









 









 





 





 








 





 





 





 





 





 





 






 






 









 









 





 





 





















 
#line 661 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h"



 

 


 

#line 686 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h"






#line 699 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h"

#line 708 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h"








#line 724 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h"




 




 



 


 
uint32_t HAL_PWREx_GetVoltageRange(void);
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection);
void HAL_PWREx_DisableBatteryCharging(void);
void HAL_PWREx_EnableInternalWakeUpLine(void);
void HAL_PWREx_DisableInternalWakeUpLine(void);
HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
void HAL_PWREx_EnablePullUpPullDownConfig(void);
void HAL_PWREx_DisablePullUpPullDownConfig(void);
void HAL_PWREx_EnableSRAM2ContentRetention(void);
void HAL_PWREx_DisableSRAM2ContentRetention(void);

void HAL_PWREx_EnablePVM1(void);
void HAL_PWREx_DisablePVM1(void);


void HAL_PWREx_EnablePVM2(void);
void HAL_PWREx_DisablePVM2(void);

void HAL_PWREx_EnablePVM3(void);
void HAL_PWREx_DisablePVM3(void);
void HAL_PWREx_EnablePVM4(void);
void HAL_PWREx_DisablePVM4(void);
HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM);

 
void HAL_PWREx_EnableLowPowerRunMode(void);
HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry);
void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry);
void HAL_PWREx_EnterSHUTDOWNMode(void);

void HAL_PWREx_PVD_PVM_IRQHandler(void);

void HAL_PWREx_PVM1Callback(void);


void HAL_PWREx_PVM2Callback(void);

void HAL_PWREx_PVM3Callback(void);
void HAL_PWREx_PVM4Callback(void);


void HAL_PWREx_EnableUCPDStandbyMode(void);
void HAL_PWREx_DisableUCPDStandbyMode(void);


void HAL_PWREx_EnableUCPDDeadBattery(void);
void HAL_PWREx_DisableUCPDDeadBattery(void);




 



 



 



 








#line 342 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h"

 



 



 

 
void HAL_PWR_DeInit(void);
void HAL_PWR_EnableBkUpAccess(void);
void HAL_PWR_DisableBkUpAccess(void);



 



 

 
HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
void HAL_PWR_EnablePVD(void);
void HAL_PWR_DisablePVD(void);


 
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);

 
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
void HAL_PWR_EnterSTANDBYMode(void);

void HAL_PWR_EnableSleepOnExit(void);
void HAL_PWR_DisableSleepOnExit(void);
void HAL_PWR_EnableSEVOnPend(void);
void HAL_PWR_DisableSEVOnPend(void);

void HAL_PWR_PVDCallback(void);




 



 



 



 








#line 309 "../Core/Inc/stm32g4xx_hal_conf.h"


































#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"
















 

 







 
#line 29 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"



 



 

 


 



 
typedef struct
{
  uint32_t Prescaler;         

 

  uint32_t CounterMode;       
 

  uint32_t Period;            




 

  uint32_t ClockDivision;     
 

  uint32_t RepetitionCounter;  








 

  uint32_t AutoReloadPreload;  
 
} TIM_Base_InitTypeDef;



 
typedef struct
{
  uint32_t OCMode;        
 

  uint32_t Pulse;         



 

  uint32_t OCPolarity;    
 

  uint32_t OCNPolarity;   

 

  uint32_t OCFastMode;    

 


  uint32_t OCIdleState;   

 

  uint32_t OCNIdleState;  

 
} TIM_OC_InitTypeDef;



 
typedef struct
{
  uint32_t OCMode;        
 

  uint32_t Pulse;         



 

  uint32_t OCPolarity;    
 

  uint32_t OCNPolarity;   

 

  uint32_t OCIdleState;   

 

  uint32_t OCNIdleState;  

 

  uint32_t ICPolarity;    
 

  uint32_t ICSelection;   
 

  uint32_t ICFilter;      
 
} TIM_OnePulse_InitTypeDef;



 
typedef struct
{
  uint32_t  ICPolarity;  
 

  uint32_t ICSelection;  
 

  uint32_t ICPrescaler;  
 

  uint32_t ICFilter;     
 
} TIM_IC_InitTypeDef;



 
typedef struct
{
  uint32_t EncoderMode;   
 

  uint32_t IC1Polarity;   
 

  uint32_t IC1Selection;  
 

  uint32_t IC1Prescaler;  
 

  uint32_t IC1Filter;     
 

  uint32_t IC2Polarity;   
 

  uint32_t IC2Selection;  
 

  uint32_t IC2Prescaler;  
 

  uint32_t IC2Filter;     
 
} TIM_Encoder_InitTypeDef;



 
typedef struct
{
  uint32_t ClockSource;     
 
  uint32_t ClockPolarity;   
 
  uint32_t ClockPrescaler;  
 
  uint32_t ClockFilter;     
 
} TIM_ClockConfigTypeDef;



 
typedef struct
{
  uint32_t ClearInputState;      
 
  uint32_t ClearInputSource;     
 
  uint32_t ClearInputPolarity;   
 
  uint32_t ClearInputPrescaler;  

 
  uint32_t ClearInputFilter;     
 
} TIM_ClearInputConfigTypeDef;





 
typedef struct
{
  uint32_t  MasterOutputTrigger;   
 
  uint32_t  MasterOutputTrigger2;  
 
  uint32_t  MasterSlaveMode;       





 
} TIM_MasterConfigTypeDef;



 
typedef struct
{
  uint32_t  SlaveMode;         
 
  uint32_t  InputTrigger;      
 
  uint32_t  TriggerPolarity;   
 
  uint32_t  TriggerPrescaler;  
 
  uint32_t  TriggerFilter;     
 

} TIM_SlaveConfigTypeDef;





 
typedef struct
{
  uint32_t OffStateRunMode;       

  uint32_t OffStateIDLEMode;      

  uint32_t LockLevel;             

  uint32_t DeadTime;              

  uint32_t BreakState;            

  uint32_t BreakPolarity;         

  uint32_t BreakFilter;           

  uint32_t BreakAFMode;           

  uint32_t Break2State;           

  uint32_t Break2Polarity;        

  uint32_t Break2Filter;          

  uint32_t Break2AFMode;          

  uint32_t AutomaticOutput;       

} TIM_BreakDeadTimeConfigTypeDef;



 
typedef enum
{
  HAL_TIM_STATE_RESET             = 0x00U,     
  HAL_TIM_STATE_READY             = 0x01U,     
  HAL_TIM_STATE_BUSY              = 0x02U,     
  HAL_TIM_STATE_TIMEOUT           = 0x03U,     
  HAL_TIM_STATE_ERROR             = 0x04U      
} HAL_TIM_StateTypeDef;



 
typedef enum
{
  HAL_TIM_CHANNEL_STATE_RESET             = 0x00U,     
  HAL_TIM_CHANNEL_STATE_READY             = 0x01U,     
  HAL_TIM_CHANNEL_STATE_BUSY              = 0x02U,     
} HAL_TIM_ChannelStateTypeDef;



 
typedef enum
{
  HAL_DMA_BURST_STATE_RESET             = 0x00U,     
  HAL_DMA_BURST_STATE_READY             = 0x01U,     
  HAL_DMA_BURST_STATE_BUSY              = 0x02U,     
} HAL_TIM_DMABurstStateTypeDef;



 
typedef enum
{
  HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,     
  HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,     
  HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,     
  HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,     
  HAL_TIM_ACTIVE_CHANNEL_5        = 0x10U,     
  HAL_TIM_ACTIVE_CHANNEL_6        = 0x20U,     
  HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U      
} HAL_TIM_ActiveChannel;



 



typedef struct

{
  TIM_TypeDef                        *Instance;          
  TIM_Base_InitTypeDef               Init;               
  HAL_TIM_ActiveChannel              Channel;            
  DMA_HandleTypeDef                  *hdma[7];          
 
  HAL_LockTypeDef                    Lock;               
  volatile HAL_TIM_StateTypeDef          State;              
  volatile HAL_TIM_ChannelStateTypeDef   ChannelState[6];    
  volatile HAL_TIM_ChannelStateTypeDef   ChannelNState[4];   
  volatile HAL_TIM_DMABurstStateTypeDef  DMABurstState;      

#line 411 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"
} TIM_HandleTypeDef;

#line 460 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"



 
 

 


 



 
#line 489 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"


 



 
#line 523 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"


 



 
#line 539 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"


 



 





 



 




 



 






 



 







 



 




 



 





 



 




 



 





 



 




 



 




 



 




 



 




 



 




 



 




 



 





 



 




 



 





 



 






 



 




 



 
#line 738 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"


 



 
#line 757 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"


 



 




 



 
#line 780 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"


 



 
#line 807 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"


 



 
#line 821 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"


 



 
#line 850 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"


 



 







 



 






 



 




 



 






 



 




 



 




 


 






 



 




 



 




 



 




 



 




 



 




 



 




 



 




 



 






 



 
#line 1011 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"


 



 
#line 1034 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"


 



 




 



 
#line 1057 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"


 



 
#line 1080 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"


 



 
#line 1108 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"


 



 







 



 






 



 




 



 
#line 1173 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"


 



 
#line 1187 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"


 



 






 



 






 



 
 

 


 




 
#line 1272 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"





 






 






 
#line 1302 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"







 
#line 1320 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"






 



















 



















 














 














 



























 



























 




















 




















 









 







 







 








 







 










 






 







 










 











 
#line 1593 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"








 



















 




















 



















 
#line 1670 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"













 
#line 1691 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"













 
#line 1712 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"













 
#line 1733 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"

















 
#line 1758 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"

















 
#line 1783 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"








 












 
















 








 
 

 


 

 




 
 

 


 
#line 1868 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"

#line 1896 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"





















































#line 1958 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"



#line 1968 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"









#line 2047 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"































































#line 2119 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"

#line 2137 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"




#line 2148 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"

#line 2155 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"

#line 2166 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"



#line 2219 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"

















#line 2262 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"







































#line 2308 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"

#line 2316 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"

#line 2331 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"













#line 2354 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"



 
 

 
#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"
















 

 







 
#line 29 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"



 



 

 


 



 

typedef struct
{
  uint32_t IC1Polarity;         
 

  uint32_t IC1Prescaler;        
 

  uint32_t IC1Filter;           
 

  uint32_t Commutation_Delay;   
 
} TIM_HallSensor_InitTypeDef;



 
typedef struct
{
  uint32_t Source;         
 
  uint32_t Enable;         
 
  uint32_t Polarity;       
 
} TIMEx_BreakInputConfigTypeDef;



 
typedef struct
{
  uint32_t Polarity;                   

  uint32_t Prescaler;                  

  uint32_t Filter;                     

  FunctionalState  FirstIndexEnable;   

  uint32_t Position;                   

  uint32_t Direction;                  

} TIMEx_EncoderIndexConfigTypeDef;



 
 

 


 



 
#line 129 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"

#line 150 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"

#line 170 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"

#line 189 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"

#line 208 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"

#line 231 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"

#line 256 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"


 



 




 



 
#line 286 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"


 



 




 



 




 



 







#line 326 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"

#line 335 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"









#line 358 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"

#line 373 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"





#line 392 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"

#line 407 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"












#line 437 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"

#line 453 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"









#line 472 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"

#line 482 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"


#line 493 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"


#line 504 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"


#line 513 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"


 



 




 



 
#line 535 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"


 



 





 



 




 



 






 



 
 

 


 







 










 












 












 













 













 














 






 
 

 


 





#line 693 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"


#line 705 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"









#line 858 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"

#line 987 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"

#line 1093 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"

#line 1911 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"
























#line 1941 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"







 
 

 


 




 
 
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);

void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);

 
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
 
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
 
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);


 




 
 
 
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);

 
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);

 
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);


 




 
 
 
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);

 
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
 
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);


 




 
 
 
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);

 
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);


 




 
 
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
                                              uint32_t  CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
                                                 uint32_t  CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
                                                  uint32_t  CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
                                                        TIM_MasterConfigTypeDef *sMasterConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
                                                TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
                                             TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
HAL_StatusTypeDef  HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel);

HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput);
HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput);
HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef *htim, uint32_t PulseWidthPrescaler,
                                                    uint32_t PulseWidth);
HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef *htim, uint32_t Source);
HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef *htim, uint32_t Deadtime);
HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef *htim, uint32_t FallingDeadtime);
HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef *htim,
                                               TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig);
HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim);


 




 
 
void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim);


 




 
 
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim,  uint32_t ChannelN);


 



 
 

 


 
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);


 
 



 



 






#line 2362 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"

 


 




 
 
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
 
HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
 
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
 
HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);


 




 
 
HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
 
HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
 
HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
 
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);


 




 
 
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
 
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
 
HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
 
HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);


 




 
 
HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
 
HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
 
HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
 
HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);


 




 
 
HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
 
HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
 
HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);


 




 
 
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
 
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
 
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
 
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
                                            uint32_t *pData2, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);


 




 
 
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);


 




 
 
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
                                                 uint32_t OutputChannel,  uint32_t InputChannel);
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
                                           uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
                                                   uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
                                                   uint32_t BurstLength,  uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
                                                  uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
                                                  uint32_t  BurstLength, uint32_t  DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);


 




 
 
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);

 








 




 
 
HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);

 
HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim,  uint32_t Channel);
HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);


 



 
 

 


 
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);

void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
void TIM_DMAError(DMA_HandleTypeDef *hdma);
void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);







 
 



 



 





#line 345 "../Core/Inc/stm32g4xx_hal_conf.h"














 
#line 375 "../Core/Inc/stm32g4xx_hal_conf.h"





#line 30 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h"



 



 

 
 



 



 







 



 



 















 



 
#line 91 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h"



 



 
#line 131 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h"



 




 






 



 





 




 






 



 


 
#line 184 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h"



 



 



 

 



 


 











































































































 



 


 



 



 




 





 













 






 
 







 






 




 











 





 





 





 








 




 








 










 

 


 

#line 457 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h"























#line 497 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h"


 



 





 

 



 



 
 
HAL_StatusTypeDef HAL_Init(void);
HAL_StatusTypeDef HAL_DeInit(void);
void HAL_MspInit(void);
void HAL_MspDeInit(void);
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);



 



 

 
void HAL_IncTick(void);
void HAL_Delay(uint32_t Delay);
uint32_t HAL_GetTick(void);
uint32_t HAL_GetTickPrio(void);
HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq);
uint32_t HAL_GetTickFreq(void);
void HAL_SuspendTick(void);
void HAL_ResumeTick(void);
uint32_t HAL_GetHalVersion(void);
uint32_t HAL_GetREVID(void);
uint32_t HAL_GetDEVID(void);



 



 

 
void HAL_DBGMCU_EnableDBGSleepMode(void);
void HAL_DBGMCU_DisableDBGSleepMode(void);
void HAL_DBGMCU_EnableDBGStopMode(void);
void HAL_DBGMCU_DisableDBGStopMode(void);
void HAL_DBGMCU_EnableDBGStandbyMode(void);
void HAL_DBGMCU_DisableDBGStandbyMode(void);



 

 


 
extern volatile uint32_t uwTick;
extern uint32_t uwTickPrio;
extern uint32_t uwTickFreq;


 



 

 
void HAL_SYSCFG_CCMSRAMErase(void);
void HAL_SYSCFG_EnableMemorySwappingBank(void);
void HAL_SYSCFG_DisableMemorySwappingBank(void);


void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
void HAL_SYSCFG_DisableVREFBUF(void);


void HAL_SYSCFG_EnableIOSwitchBooster(void);
void HAL_SYSCFG_DisableIOSwitchBooster(void);
void HAL_SYSCFG_EnableIOSwitchVDD(void);
void HAL_SYSCFG_DisableIOSwitchVDD(void);

void HAL_SYSCFG_CCMSRAM_WriteProtectionEnable(uint32_t Page);



 



 



 



 







#line 31 "../Core/Inc/main.h"

#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"
















 

 







 
#line 29 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"



 





 

 
 

 


 

 
 
 
 

 
 










 
 
#line 83 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"



 
 
 
 

 
 










 
 







 
 
 
 


 
 
 





 
 
 





 





 
 
 
 


 
 
 





 
 
 





 








 
 
 
 
 
 
 
 





 


 




 
 








 
 
#line 224 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"

 
 
#line 246 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"

 
 
#line 268 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"


 
 
 
 
 
 
#line 283 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"

 
 
 
 
 
 
 
 

 




 
 











 
#line 320 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"

 
 
#line 329 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"


 







 



 
 


 








 


 


 








 





 


 



 










 
typedef struct
{
  uint32_t CommonClock;                 





 


  uint32_t Multimode;                   


 

  uint32_t MultiDMATransfer;            


 

  uint32_t MultiTwoSamplingDelay;       


 


} LL_ADC_CommonInitTypeDef;




















 
typedef struct
{
  uint32_t Resolution;                  


 

  uint32_t DataAlignment;               


 

  uint32_t LowPowerMode;                


 

} LL_ADC_InitTypeDef;



















 
typedef struct
{
  uint32_t TriggerSource;               





 

  uint32_t SequencerLength;             


 

  uint32_t SequencerDiscont;            




 

  uint32_t ContinuousMode;              



 

  uint32_t DMATransfer;                 


 

  uint32_t Overrun;                     



 

} LL_ADC_REG_InitTypeDef;



















 
typedef struct
{
  uint32_t TriggerSource;               





 

  uint32_t SequencerLength;             


 

  uint32_t SequencerDiscont;            




 

  uint32_t TrigAuto;                    



 

} LL_ADC_INJ_InitTypeDef;



 


 


 




 
#line 622 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"


 




 
#line 641 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"


 



 
 
 
 






 



 
#line 677 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"


 



 
 
 
 
 
 






 



 






 



 




 



 




 



 






 



 




 



 




 



 




 


 





 



 
#line 806 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"


 



 
#line 920 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"


 



 





 



 
#line 943 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"


 



 




 



 





 




 




 




 




 



 
#line 1005 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"


 



 
#line 1021 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"


 



 
#line 1044 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"


 



 
#line 1154 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"


 



 





 



 




 



 





 



 






 



 




 



 






 



 
#line 1229 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"


 



 





 



 





 



 
#line 1350 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"


 



 





 



 
#line 1375 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"


 



 







 



 




 



 
#line 1411 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"


 



 
#line 1427 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"


 




 
#line 1443 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"


 



 







 



 
#line 1474 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"


 



 





 










 

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

 
 
 
 


 
 
 
 


 
 
 
 


 
 
 
 
 
 
 




 



 


 


 



 







 







 



 



 





















































 
#line 1649 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"





















































 
#line 1717 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"






























































 














































































 








































 
#line 2014 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"




































































































































































 
#line 2188 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"




















 





















 














 















 
















 
















 
#line 2319 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"










 
#line 2344 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"
















 
#line 2391 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"













 




















 
#line 2433 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"
















 
#line 2456 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"

























 
#line 2489 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"













































 
#line 2548 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"












































 
#line 2609 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"



 



 


 


 



 
 
 
 






























 

static __inline uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
{
  uint32_t data_reg_addr;

  if (Register == (0x00000000UL))
  {
     
    data_reg_addr = (uint32_t) &(ADCx->DR);
  }
  else  
  {
     
    data_reg_addr = (uint32_t) &((((((ADCx) == ((ADC_TypeDef *) (((0x40000000UL) + 0x08000000UL) + 0x08000000UL))) || ((ADCx) == ((ADC_TypeDef *) (((0x40000000UL) + 0x08000000UL) + 0x08000100UL)))) ? ( (((ADC_Common_TypeDef *) (((0x40000000UL) + 0x08000000UL) + 0x08000300UL))) ) : ( (((ADC_Common_TypeDef *) (((0x40000000UL) + 0x08000000UL) + 0x08000700UL))) ) ))->CDR);
  }

  return data_reg_addr;
}
#line 2689 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"



 



 


































 
static __inline void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
{
  (((ADCxy_COMMON->CCR)) = ((((((ADCxy_COMMON->CCR))) & (~((0x3UL << (16U)) | (0xFUL << (18U))))) | (CommonClock))));
}























 
static __inline uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
{
  return (uint32_t)(((ADCxy_COMMON->CCR) & ((0x3UL << (16U)) | (0xFUL << (18U)))));
}































 
static __inline void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
{
  (((ADCxy_COMMON->CCR)) = ((((((ADCxy_COMMON->CCR))) & (~((0x1UL << (22U)) | (0x1UL << (23U)) | (0x1UL << (24U))))) | (PathInternal))));
}






























 
static __inline void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
{
  ((ADCxy_COMMON->CCR) |= (PathInternal));
}



















 
static __inline void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
{
  ((ADCxy_COMMON->CCR) &= ~(PathInternal));
}

















 
static __inline uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
{
  return (uint32_t)(((ADCxy_COMMON->CCR) & ((0x1UL << (22U)) | (0x1UL << (23U)) | (0x1UL << (24U)))));
}



 



 































 
static __inline void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
{
  (((ADCx->CALFACT)) = ((((((ADCx->CALFACT))) & (~(SingleDiff & ((0x7FUL << (16U)) | (0x7FUL << (0U)))))) | (CalibrationFactor << (((SingleDiff & (0x00010000UL)) >> ((16UL) - 4UL)) & ~(SingleDiff & (0x7FUL << (0U))))))));


}
















 
static __inline uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
{
   
   
   
   
  return (uint32_t)(((ADCx->CALFACT) & ((SingleDiff & ((0x7FUL << (16U)) | (0x7FUL << (0U)))))) >> ((SingleDiff & (0x00010000UL)) >>

                                                                                  ((16UL) - 4UL)));
}

















 
static __inline void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
{
  (((ADCx->CFGR)) = ((((((ADCx->CFGR))) & (~((0x3UL << (3U))))) | (Resolution))));
}












 
static __inline uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
{
  return (uint32_t)(((ADCx->CFGR) & ((0x3UL << (3U)))));
}















 
static __inline void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
{
  (((ADCx->CFGR)) = ((((((ADCx->CFGR))) & (~((0x1UL << (15U))))) | (DataAlignment))));
}










 
static __inline uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
{
  return (uint32_t)(((ADCx->CFGR) & ((0x1UL << (15U)))));
}



















































 
static __inline void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
{
  (((ADCx->CFGR)) = ((((((ADCx->CFGR))) & (~((0x1UL << (14U))))) | (LowPowerMode))));
}














































 
static __inline uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
{
  return (uint32_t)(((ADCx->CFGR) & ((0x1UL << (14U)))));
}




















































































 
static __inline void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
{
  volatile uint32_t *preg = ((volatile uint32_t *)((uint32_t) ((uint32_t)(&(ADCx->OFR1)) + ((Offsety) << 2UL))));

  (((*preg)) = ((((((*preg))) & (~((0x1UL << (31U)) | (0x1FUL << (26U)) | (0xFFFUL << (0U))))) | ((0x1UL << (31U)) | (Channel & ((0x1FUL << (26U)))) | OffsetLevel))));


}










































































 
static __inline uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
{
  const volatile uint32_t *preg = ((volatile uint32_t *)((uint32_t) ((uint32_t)(&(ADCx->OFR1)) + ((Offsety) << 2UL))));

  return (uint32_t) ((*preg) & ((0x1FUL << (26U))));
}



















 
static __inline uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
{
  const volatile uint32_t *preg = ((volatile uint32_t *)((uint32_t) ((uint32_t)(&(ADCx->OFR1)) + ((Offsety) << 2UL))));

  return (uint32_t) ((*preg) & ((0xFFFUL << (0U))));
}


























 
static __inline void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
{
  volatile uint32_t *preg = ((volatile uint32_t *)((uint32_t) ((uint32_t)(&(ADCx->OFR1)) + ((Offsety) << 2UL))));

  (((*preg)) = ((((((*preg))) & (~((0x1UL << (31U))))) | (OffsetState))));


}

















 
static __inline uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety)
{
  const volatile uint32_t *preg = ((volatile uint32_t *)((uint32_t) ((uint32_t)(&(ADCx->OFR1)) + ((Offsety) << 2UL))));

  return (uint32_t) ((*preg) & ((0x1UL << (31U))));
}






















 
static __inline void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
{
  volatile uint32_t *preg = ((volatile uint32_t *)((uint32_t) ((uint32_t)(&(ADCx->OFR1)) + ((Offsety) << 2UL))));

  (((*preg)) = ((((((*preg))) & (~((0x1UL << (24U))))) | (OffsetSign))));


}

















 
static __inline uint32_t LL_ADC_GetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety)
{
  const volatile uint32_t *preg = ((volatile uint32_t *)((uint32_t) ((uint32_t)(&(ADCx->OFR1)) + ((Offsety) << 2UL))));

  return (uint32_t) ((*preg) & ((0x1UL << (24U))));
}






















 
static __inline void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSaturation)
{
  volatile uint32_t *preg = ((volatile uint32_t *)((uint32_t) ((uint32_t)(&(ADCx->OFR1)) + ((Offsety) << 2UL))));

  (((*preg)) = ((((((*preg))) & (~((0x1UL << (25U))))) | (OffsetSaturation))));


}

















 
static __inline uint32_t LL_ADC_GetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety)
{
  const volatile uint32_t *preg = ((volatile uint32_t *)((uint32_t) ((uint32_t)(&(ADCx->OFR1)) + ((Offsety) << 2UL))));

  return (uint32_t) ((*preg) & ((0x1UL << (25U))));
}




















 
static __inline void LL_ADC_SetGainCompensation(ADC_TypeDef *ADCx, uint32_t GainCompensation)
{
  (((ADCx->GCOMP)) = ((((((ADCx->GCOMP))) & (~((0x3FFFUL << (0U))))) | (GainCompensation))));
  (((ADCx->CFGR2)) = ((((((ADCx->CFGR2))) & (~((0x1UL << (16U))))) | (((GainCompensation == 0UL) ? 0UL : 1UL) << (16U)))));
}









 
static __inline uint32_t LL_ADC_GetGainCompensation(ADC_TypeDef *ADCx)
{
  return ((((ADCx->CFGR2) & ((0x1UL << (16U)))) == (0x1UL << (16U))) ? ((ADCx->GCOMP) & ((0x3FFFUL << (0U)))) : 0UL);
}















 
static __inline void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig)
{
  (((ADCx->SMPR1)) = ((((((ADCx->SMPR1))) & (~((0x1UL << (31U))))) | (SamplingTimeCommonConfig))));
}









 
static __inline uint32_t LL_ADC_GetSamplingTimeCommonConfig(ADC_TypeDef *ADCx)
{
  return (uint32_t)(((ADCx->SMPR1) & ((0x1UL << (31U)))));
}




 



 


































































 
static __inline void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
{
  (((ADCx->CFGR)) = ((((((ADCx->CFGR))) & (~((0x3UL << (10U)) | (0x1FUL << (5U))))) | (TriggerSource))));
}





























































 
static __inline uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
{
  volatile uint32_t TriggerSource = ((ADCx->CFGR) & ((0x1FUL << (5U)) | (0x3UL << (10U))));

   
   
  uint32_t ShiftExten = ((TriggerSource & (0x3UL << (10U))) >> (((10U)) - 2UL));

   
   
  return ((TriggerSource
           & (((((0x00000000UL) & (0x1FUL << (5U))) << (4U * 0UL)) | (((0x1FUL << (5U))) << (4U * 1UL)) | (((0x1FUL << (5U))) << (4U * 2UL)) | (((0x1FUL << (5U))) << (4U * 3UL)) ) >> ShiftExten) & (0x1FUL << (5U)))
          | ((((((0x00000000UL) & (0x3UL << (10U))) << (4U * 0UL)) | ((((0x1UL << (10U)))) << (4U * 1UL)) | ((((0x1UL << (10U)))) << (4U * 2UL)) | ((((0x1UL << (10U)))) << (4U * 3UL)) ) >> ShiftExten) & (0x3UL << (10U)))
         );
}











 
static __inline uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
{
  return ((((ADCx->CFGR) & ((0x3UL << (10U)))) == ((0x00000000UL) & (0x3UL << (10U)))) ? 1UL : 0UL);
}















 
static __inline void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
{
  (((ADCx->CFGR)) = ((((((ADCx->CFGR))) & (~((0x3UL << (10U))))) | (ExternalTriggerEdge))));
}










 
static __inline uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
{
  return (uint32_t)(((ADCx->CFGR) & ((0x3UL << (10U)))));
}


















 
static __inline void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx, uint32_t SamplingMode)
{
  (((ADCx->CFGR2)) = ((((((ADCx->CFGR2))) & (~((0x1UL << (26U)) | (0x1UL << (27U))))) | (SamplingMode))));
}










 
static __inline uint32_t LL_ADC_REG_GetSamplingMode(ADC_TypeDef *ADCx)
{
  return (uint32_t)(((ADCx->CFGR2) & ((0x1UL << (26U)) | (0x1UL << (27U)))));
}






















































 
static __inline void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
{
  (((ADCx->SQR1)) = ((((((ADCx->SQR1))) & (~((0xFUL << (0U))))) | (SequencerNbRanks))));
}

















































 
static __inline uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
{
  return (uint32_t)(((ADCx->SQR1) & ((0xFUL << (0U)))));
}



























 
static __inline void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
{
  (((ADCx->CFGR)) = ((((((ADCx->CFGR))) & (~((0x1UL << (16U)) | (0x7UL << (17U))))) | (SeqDiscont))));
}


















 
static __inline uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
{
  return (uint32_t)(((ADCx->CFGR) & ((0x1UL << (16U)) | (0x7UL << (17U)))));
}


































































































 
static __inline void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
{
   
   
   
   
  volatile uint32_t *preg = ((volatile uint32_t *)((uint32_t) ((uint32_t)(&(ADCx->SQR1)) + ((((Rank & ((0x00000000UL) | (0x00000100UL) | (0x00000200UL) | (0x00000300UL))) >> (8UL))) << 2UL))));

  (((*preg)) = ((((((*preg))) & (~(((0x1FUL << (0U))) << (Rank & (((0x1FUL << (0U)))))))) | (((Channel & ((0x1FUL << (26U)))) >> ((26U))) << (Rank & (((0x1FUL << (0U)))))))));


}




































































































 
static __inline uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
{
  const volatile uint32_t *preg = ((volatile uint32_t *)((uint32_t) ((uint32_t)(&(ADCx->SQR1)) + ((((Rank & ((0x00000000UL) | (0x00000100UL) | (0x00000200UL) | (0x00000300UL))) >> (8UL))) << 2UL))));

  return (uint32_t)((((*preg) & (((0x1FUL << (0U))) << (Rank & (((0x1FUL << (0U)))))))

                     >> (Rank & (((0x1FUL << (0U)))))) << ((26U))
                   );
}



















 
static __inline void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
{
  (((ADCx->CFGR)) = ((((((ADCx->CFGR))) & (~((0x1UL << (13U))))) | (Continuous))));
}












 
static __inline uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
{
  return (uint32_t)(((ADCx->CFGR) & ((0x1UL << (13U)))));
}



































 
static __inline void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
{
  (((ADCx->CFGR)) = ((((((ADCx->CFGR))) & (~((0x1UL << (0U)) | (0x1UL << (1U))))) | (DMATransfer))));
}






























 
static __inline uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
{
  return (uint32_t)(((ADCx->CFGR) & ((0x1UL << (0U)) | (0x1UL << (1U)))));
}




















 
static __inline void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
{
  (((ADCx->CFGR)) = ((((((ADCx->CFGR))) & (~((0x1UL << (12U))))) | (Overrun))));
}









 
static __inline uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
{
  return (uint32_t)(((ADCx->CFGR) & ((0x1UL << (12U)))));
}



 



 

































































 
static __inline void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
{
  (((ADCx->JSQR)) = ((((((ADCx->JSQR))) & (~((0x1FUL << (2U)) | (0x3UL << (7U))))) | (TriggerSource))));
}




























































 
static __inline uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
{
  volatile uint32_t TriggerSource = ((ADCx->JSQR) & ((0x1FUL << (2U)) | (0x3UL << (7U))));

   
   
  uint32_t ShiftJexten = ((TriggerSource & (0x3UL << (7U))) >> (((7U)) - 2UL));

   
   
  return ((TriggerSource
           & (((((0x00000000UL) & (0x1FUL << (2U))) << (4U * 0UL)) | (((0x1FUL << (2U))) << (4U * 1UL)) | (((0x1FUL << (2U))) << (4U * 2UL)) | (((0x1FUL << (2U))) << (4U * 3UL)) ) >> ShiftJexten) & (0x1FUL << (2U)))
          | ((((((0x00000000UL) & (0x3UL << (7U))) << (4U * 0UL)) | ((((0x1UL << (7U)))) << (4U * 1UL)) | ((((0x1UL << (7U)))) << (4U * 2UL)) | ((((0x1UL << (7U)))) << (4U * 3UL)) ) >> ShiftJexten) & (0x3UL << (7U)))
         );
}











 
static __inline uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
{
  return ((((ADCx->JSQR) & ((0x3UL << (7U)))) == ((0x00000000UL) & (0x3UL << (7U)))) ? 1UL : 0UL);
}















 
static __inline void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
{
  (((ADCx->JSQR)) = ((((((ADCx->JSQR))) & (~((0x3UL << (7U))))) | (ExternalTriggerEdge))));
}










 
static __inline uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
{
  return (uint32_t)(((ADCx->JSQR) & ((0x3UL << (7U)))));
}





















 
static __inline void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
{
  (((ADCx->JSQR)) = ((((((ADCx->JSQR))) & (~((0x3UL << (0U))))) | (SequencerNbRanks))));
}
















 
static __inline uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
{
  return (uint32_t)(((ADCx->JSQR) & ((0x3UL << (0U)))));
}













 
static __inline void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
{
  (((ADCx->CFGR)) = ((((((ADCx->CFGR))) & (~((0x1UL << (20U))))) | (SeqDiscont))));
}










 
static __inline uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
{
  return (uint32_t)(((ADCx->CFGR) & ((0x1UL << (20U)))));
}





































































 
static __inline void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
{
   
   
   
   
  (((ADCx->JSQR)) = ((((((ADCx->JSQR))) & (~((((0x1FUL << (26U))) >> ((26U))) << (Rank & (((0x1FUL << (0U)))))))) | (((Channel & ((0x1FUL << (26U)))) >> ((26U))) << (Rank & (((0x1FUL << (0U)))))))));


}








































































 
static __inline uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
{
  return (uint32_t)((((ADCx->JSQR) & ((((0x1FUL << (26U))) >> ((26U))) << (Rank & (((0x1FUL << (0U)))))))

                     >> (Rank & (((0x1FUL << (0U)))))) << ((26U))
                   );
}






























 
static __inline void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
{
  (((ADCx->CFGR)) = ((((((ADCx->CFGR))) & (~((0x1UL << (25U))))) | (TrigAuto))));
}









 
static __inline uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
{
  return (uint32_t)(((ADCx->CFGR) & ((0x1UL << (25U)))));
}









































 
static __inline void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
{
  (((ADCx->CFGR)) = ((((((ADCx->CFGR))) & (~((0x1UL << (21U)) | (0x1UL << (31U))))) | (QueueMode))));
}










 
static __inline uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
{
  return (uint32_t)(((ADCx->CFGR) & ((0x1UL << (21U)) | (0x1UL << (31U)))));
}





































































































































































































































































 
static __inline void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
                                                   uint32_t TriggerSource,
                                                   uint32_t ExternalTriggerEdge,
                                                   uint32_t SequencerNbRanks,
                                                   uint32_t Rank1_Channel,
                                                   uint32_t Rank2_Channel,
                                                   uint32_t Rank3_Channel,
                                                   uint32_t Rank4_Channel)
{
   
   
   
   
   
   
  uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != (0x00000000UL)) ? 1UL : 0UL);
  (((ADCx->JSQR)) = ((((((ADCx->JSQR))) & (~((0x1FUL << (2U)) | (0x3UL << (7U)) | (0x1FUL << (27U)) | (0x1FUL << (21U)) | (0x1FUL << (15U)) | (0x1FUL << (9U)) | (0x3UL << (0U))))) | ((TriggerSource & (0x1FUL << (2U))) | (ExternalTriggerEdge * (is_trigger_not_sw)) | (((Rank4_Channel & ((0x1FUL << (26U)))) >> ((26U))) << (((0x00000300UL) | ((27U))) & (((0x1FUL << (0U)))))) | (((Rank3_Channel & ((0x1FUL << (26U)))) >> ((26U))) << (((0x00000200UL) | ((21U))) & (((0x1FUL << (0U)))))) | (((Rank2_Channel & ((0x1FUL << (26U)))) >> ((26U))) << (((0x00000100UL) | ((15U))) & (((0x1FUL << (0U)))))) | (((Rank1_Channel & ((0x1FUL << (26U)))) >> ((26U))) << (((0x00000000UL) | ((9U))) & (((0x1FUL << (0U)))))) | SequencerNbRanks))));
#line 5217 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h"
}



 



 







































































































 
static __inline void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
{
   
   
   
   
  volatile uint32_t *preg = ((volatile uint32_t *)((uint32_t) ((uint32_t)(&(ADCx->SMPR1)) + ((((Channel & ((0x00000000UL) | (0x02000000UL))) >> (25UL))) << 2UL))));

  (((*preg)) = ((((((*preg))) & (~((0x7UL << (0U)) << ((Channel & (0x01F00000UL)) >> (20UL))))) | (SamplingTime << ((Channel & (0x01F00000UL)) >> (20UL))))));


}























































































 
static __inline uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
{
  const volatile uint32_t *preg = ((volatile uint32_t *)((uint32_t) ((uint32_t)(&(ADCx->SMPR1)) + ((((Channel & ((0x00000000UL) | (0x02000000UL))) >> (25UL))) << 2UL))));

  return (uint32_t)(((*preg) & ((0x7UL << (0U)) << ((Channel & (0x01F00000UL)) >> (20UL))))

                    >> ((Channel & (0x01F00000UL)) >> (20UL))
                   );
}























































 
static __inline void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
{
   
   
   
  
  if (SingleDiff == ((0x1UL << (30U)) | (0x7FUL << (16U))))
  {
    ((ADCx->DIFSEL) |= (Channel & (((0x7FFFFUL << (0U))))));

  }
  else
  {
    ((ADCx->DIFSEL) &= ~(Channel & (((0x7FFFFUL << (0U))))));

  }
}















































 
static __inline uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
{
  return (uint32_t)(((ADCx->DIFSEL) & ((Channel & (((0x7FFFFUL << (0U))))))));
}



 



 
























































































































































 
static __inline void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
{
   
   
   
   
  volatile uint32_t *preg = ((volatile uint32_t *)((uint32_t) ((uint32_t)(&(ADCx->CFGR)) + ((((AWDy & ((0x00000000UL) | (0x00100000UL) | (0x00200000UL))) >> (20UL)) + ((AWDy & ((0x00001UL << (0U)))) * (0x00000024UL))) << 2UL))));


  (((*preg)) = ((((((*preg))) & (~((AWDy & (((0x1FUL << (26U)) | (0x1UL << (24U)) | (0x1UL << (23U)) | (0x1UL << (22U))) | ((0x7FFFFUL << (0U)))))))) | (AWDChannelGroup & AWDy))));


}


























































































































 
static __inline uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
{
  const volatile uint32_t *preg = ((volatile uint32_t *)((uint32_t) ((uint32_t)(&(ADCx->CFGR)) + ((((AWDy & ((0x00000000UL) | (0x00100000UL) | (0x00200000UL))) >> (20UL)) + ((AWDy & ((0x00001UL << (0U)))) * (0x00000024UL))) << 2UL))));


  uint32_t AnalogWDMonitChannels = (((*preg) & (AWDy)) & (((0x1FUL << (26U)) | (0x1UL << (24U)) | (0x1UL << (23U)) | (0x1UL << (22U))) | ((0x7FFFFUL << (0U)))));

   
   
   
   
  if (AnalogWDMonitChannels != 0UL)
  {
    if (AWDy == (((0x1FUL << (26U)) | (0x1UL << (24U)) | (0x1UL << (23U)) | (0x1UL << (22U))) | (0x00000000UL)))
    {
      if ((AnalogWDMonitChannels & (0x1UL << (22U))) == 0UL)
      {
         
        AnalogWDMonitChannels = ((AnalogWDMonitChannels
                                  | (((0x7FFFFUL << (0U))))
                                 )
                                 & (~((0x1FUL << (26U))))
                                );
      }
      else
      {
         
        AnalogWDMonitChannels = (AnalogWDMonitChannels
                                 | ((0x00001UL << (0U)) << (AnalogWDMonitChannels >> (26U)))
                                );
      }
    }
    else
    {
      if ((AnalogWDMonitChannels & ((0x7FFFFUL << (0U)))) == ((0x7FFFFUL << (0U))))
      {
         
        AnalogWDMonitChannels = (((0x7FFFFUL << (0U)))
                                 | (((0x1UL << (24U)) | (0x1UL << (23U))))
                                );
      }
      else
      {
         
         
        AnalogWDMonitChannels = (AnalogWDMonitChannels
                                 | ((0x1UL << (24U)) | (0x1UL << (23U)) | (0x1UL << (22U)))
                                 | (((((AnalogWDMonitChannels) & ((0x7FFFFUL << (0U)))) == 0UL) ? ( ((AnalogWDMonitChannels) & ((0x1FUL << (26U)))) >> ((26U)) ) : ( (uint32_t)(__clz(__rbit((AnalogWDMonitChannels)))) ) ) << (26U))
                                );
      }
    }
  }

  return AnalogWDMonitChannels;
}
















































 
static __inline void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
                                                     uint32_t AWDThresholdLowValue)
{
   
   
   
   
   
  volatile uint32_t *preg = ((volatile uint32_t *)((uint32_t) ((uint32_t)(&(ADCx->TR1)) + ((((AWDy & (((0x00000000UL)) | ((0x00100000UL)) | ((0x00200000UL)))) >> ((20UL)))) << 2UL))));

  (((*preg)) = ((((((*preg))) & (~((0xFFFUL << (16U)) | (0xFFFUL << (0U))))) | ((AWDThresholdHighValue << ((16U))) | AWDThresholdLowValue))));


}






















































 
static __inline void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
                                                  uint32_t AWDThresholdValue)
{
   
   
   
   
   
  volatile uint32_t *preg = ((volatile uint32_t *)((uint32_t) ((uint32_t)(&(ADCx->TR1)) + ((((AWDy & (((0x00000000UL)) | ((0x00100000UL)) | ((0x00200000UL)))) >> ((20UL)))) << 2UL))));


  (((*preg)) = ((((((*preg))) & (~(AWDThresholdsHighLow))) | (AWDThresholdValue << ((AWDThresholdsHighLow & (0x00010000UL)) >> ((16UL) - 4UL))))));


}




























 
static __inline uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
{
  const volatile uint32_t *preg = ((volatile uint32_t *)((uint32_t) ((uint32_t)(&(ADCx->TR1)) + ((((AWDy & (((0x00000000UL)) | ((0x00100000UL)) | ((0x00200000UL)))) >> ((20UL)))) << 2UL))));


  return (uint32_t)(((*preg) & ((AWDThresholdsHighLow | (0xFFFUL << (0U)))))

                    >> (((AWDThresholdsHighLow & (0x00010000UL)) >> ((16UL) - 4UL))
                        & ~(AWDThresholdsHighLow & (0xFFFUL << (0U)))));
}























 
static __inline void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t FilteringConfig)
{
   
  (void)(AWDy);
  (((ADCx->TR1)) = ((((((ADCx->TR1))) & (~((0x7UL << (12U))))) | (FilteringConfig))));
}


















 
static __inline uint32_t LL_ADC_GetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy)
{
   
  (void)(AWDy);
  return (uint32_t)(((ADCx->TR1) & ((0x7UL << (12U)))));
}



 



 

























 
static __inline void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
{
  (((ADCx->CFGR2)) = ((((((ADCx->CFGR2))) & (~((0x1UL << (0U)) | (0x1UL << (1U)) | (0x1UL << (10U))))) | (OvsScope))));
}




















 
static __inline uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
{
  return (uint32_t)(((ADCx->CFGR2) & ((0x1UL << (0U)) | (0x1UL << (1U)) | (0x1UL << (10U)))));
}






















 
static __inline void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
{
  (((ADCx->CFGR2)) = ((((((ADCx->CFGR2))) & (~((0x1UL << (9U))))) | (OverSamplingDiscont))));
}














 
static __inline uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
{
  return (uint32_t)(((ADCx->CFGR2) & ((0x1UL << (9U)))));
}


































 
static __inline void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
{
  (((ADCx->CFGR2)) = ((((((ADCx->CFGR2))) & (~(((0xFUL << (5U)) | (0x7UL << (2U)))))) | ((Shift | Ratio)))));
}















 
static __inline uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
{
  return (uint32_t)(((ADCx->CFGR2) & ((0x7UL << (2U)))));
}
















 
static __inline uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
{
  return (uint32_t)(((ADCx->CFGR2) & ((0xFUL << (5U)))));
}



 



 



























 
static __inline void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
{
  (((ADCxy_COMMON->CCR)) = ((((((ADCxy_COMMON->CCR))) & (~((0x1FUL << (0U))))) | (Multimode))));
}



















 
static __inline uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
{
  return (uint32_t)(((ADCxy_COMMON->CCR) & ((0x1FUL << (0U)))));
}














































 
static __inline void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
{
  (((ADCxy_COMMON->CCR)) = ((((((ADCxy_COMMON->CCR))) & (~((0x3UL << (14U)) | (0x1UL << (13U))))) | (MultiDMATransfer))));
}









































 
static __inline uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
{
  return (uint32_t)(((ADCxy_COMMON->CCR) & ((0x3UL << (14U)) | (0x1UL << (13U)))));
}



































 
static __inline void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
{
  (((ADCxy_COMMON->CCR)) = ((((((ADCxy_COMMON->CCR))) & (~((0xFUL << (8U))))) | (MultiTwoSamplingDelay))));
}























 
static __inline uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
{
  return (uint32_t)(((ADCxy_COMMON->CCR) & ((0xFUL << (8U)))));
}




 


 













 
static __inline void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
{
   
   
   
  (((ADCx->CR)) = ((((((ADCx->CR))) & (~(((0x1UL << (31U)) | (0x1UL << (5U)) | (0x1UL << (4U)) | (0x1UL << (3U)) | (0x1UL << (2U)) | (0x1UL << (1U)) | (0x1UL << (0U)))))) | ((0x1UL << (29U))))));


}













 
static __inline void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
{
   
   
   
  ((ADCx->CR) &= ~(((0x1UL << (29U)) | ((0x1UL << (31U)) | (0x1UL << (5U)) | (0x1UL << (4U)) | (0x1UL << (3U)) | (0x1UL << (2U)) | (0x1UL << (1U)) | (0x1UL << (0U))))));
}






 
static __inline uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
{
  return ((((ADCx->CR) & ((0x1UL << (29U)))) == ((0x1UL << (29U)))) ? 1UL : 0UL);
}














 
static __inline void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
{
   
   
   
  (((ADCx->CR)) = ((((((ADCx->CR))) & (~(((0x1UL << (31U)) | (0x1UL << (5U)) | (0x1UL << (4U)) | (0x1UL << (3U)) | (0x1UL << (2U)) | (0x1UL << (1U)) | (0x1UL << (0U)))))) | ((0x1UL << (28U))))));


}









 
static __inline void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
{
  ((ADCx->CR) &= ~(((0x1UL << (28U)) | ((0x1UL << (31U)) | (0x1UL << (5U)) | (0x1UL << (4U)) | (0x1UL << (3U)) | (0x1UL << (2U)) | (0x1UL << (1U)) | (0x1UL << (0U))))));
}






 
static __inline uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
{
  return ((((ADCx->CR) & ((0x1UL << (28U)))) == ((0x1UL << (28U)))) ? 1UL : 0UL);
}
















 
static __inline void LL_ADC_Enable(ADC_TypeDef *ADCx)
{
   
   
   
  (((ADCx->CR)) = ((((((ADCx->CR))) & (~(((0x1UL << (31U)) | (0x1UL << (5U)) | (0x1UL << (4U)) | (0x1UL << (3U)) | (0x1UL << (2U)) | (0x1UL << (1U)) | (0x1UL << (0U)))))) | ((0x1UL << (0U))))));


}










 
static __inline void LL_ADC_Disable(ADC_TypeDef *ADCx)
{
   
   
   
  (((ADCx->CR)) = ((((((ADCx->CR))) & (~(((0x1UL << (31U)) | (0x1UL << (5U)) | (0x1UL << (4U)) | (0x1UL << (3U)) | (0x1UL << (2U)) | (0x1UL << (1U)) | (0x1UL << (0U)))))) | ((0x1UL << (1U))))));


}









 
static __inline uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
{
  return ((((ADCx->CR) & ((0x1UL << (0U)))) == ((0x1UL << (0U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
{
  return ((((ADCx->CR) & ((0x1UL << (1U)))) == ((0x1UL << (1U)))) ? 1UL : 0UL);
}























 
static __inline void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)
{
   
   
   
  (((ADCx->CR)) = ((((((ADCx->CR))) & (~((0x1UL << (30U)) | ((0x1UL << (31U)) | (0x1UL << (5U)) | (0x1UL << (4U)) | (0x1UL << (3U)) | (0x1UL << (2U)) | (0x1UL << (1U)) | (0x1UL << (0U)))))) | ((0x1UL << (31U)) | (SingleDiff & ((0x1UL << (30U))))))));


}






 
static __inline uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
{
  return ((((ADCx->CR) & ((0x1UL << (31U)))) == ((0x1UL << (31U)))) ? 1UL : 0UL);
}



 



 


















 
static __inline void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
{
   
   
   
  (((ADCx->CR)) = ((((((ADCx->CR))) & (~(((0x1UL << (31U)) | (0x1UL << (5U)) | (0x1UL << (4U)) | (0x1UL << (3U)) | (0x1UL << (2U)) | (0x1UL << (1U)) | (0x1UL << (0U)))))) | ((0x1UL << (2U))))));


}










 
static __inline void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
{
   
   
   
  (((ADCx->CR)) = ((((((ADCx->CR))) & (~(((0x1UL << (31U)) | (0x1UL << (5U)) | (0x1UL << (4U)) | (0x1UL << (3U)) | (0x1UL << (2U)) | (0x1UL << (1U)) | (0x1UL << (0U)))))) | ((0x1UL << (4U))))));


}






 
static __inline uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
{
  return ((((ADCx->CR) & ((0x1UL << (2U)))) == ((0x1UL << (2U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
{
  return ((((ADCx->CR) & ((0x1UL << (4U)))) == ((0x1UL << (4U)))) ? 1UL : 0UL);
}















 
static __inline void LL_ADC_REG_StartSamplingPhase(ADC_TypeDef *ADCx)
{
  ((ADCx->CFGR2) |= ((0x1UL << (25U))));
}

















 
static __inline void LL_ADC_REG_StopSamplingPhase(ADC_TypeDef *ADCx)
{
  ((ADCx->CFGR2) &= ~((0x1UL << (25U))));
}









 
static __inline uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
{
  return (uint32_t)(((ADCx->DR) & ((0xFFFFUL << (0U)))));
}










 
static __inline uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
{
  return (uint16_t)(((ADCx->DR) & ((0xFFFFUL << (0U)))));
}










 
static __inline uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
{
  return (uint16_t)(((ADCx->DR) & ((0xFFFFUL << (0U)))));
}










 
static __inline uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
{
  return (uint8_t)(((ADCx->DR) & ((0xFFFFUL << (0U)))));
}










 
static __inline uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
{
  return (uint8_t)(((ADCx->DR) & ((0xFFFFUL << (0U)))));
}






















 
static __inline uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
{
  return (uint32_t)(((ADCxy_COMMON->CDR) & (ConversionData))

                    >> ((__clz(__rbit(ConversionData))) & 0x1FUL)
                   );
}




 



 


















 
static __inline void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
{
   
   
   
  (((ADCx->CR)) = ((((((ADCx->CR))) & (~(((0x1UL << (31U)) | (0x1UL << (5U)) | (0x1UL << (4U)) | (0x1UL << (3U)) | (0x1UL << (2U)) | (0x1UL << (1U)) | (0x1UL << (0U)))))) | ((0x1UL << (3U))))));


}










 
static __inline void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
{
   
   
   
  (((ADCx->CR)) = ((((((ADCx->CR))) & (~(((0x1UL << (31U)) | (0x1UL << (5U)) | (0x1UL << (4U)) | (0x1UL << (3U)) | (0x1UL << (2U)) | (0x1UL << (1U)) | (0x1UL << (0U)))))) | ((0x1UL << (5U))))));


}






 
static __inline uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
{
  return ((((ADCx->CR) & ((0x1UL << (3U)))) == ((0x1UL << (3U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)
{
  return ((((ADCx->CR) & ((0x1UL << (5U)))) == ((0x1UL << (5U)))) ? 1UL : 0UL);
}

















 
static __inline uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
{
  const volatile uint32_t *preg = ((volatile uint32_t *)((uint32_t) ((uint32_t)(&(ADCx->JDR1)) + ((((Rank & ((0x00000000UL) | (0x00000100UL) | (0x00000200UL) | (0x00000300UL))) >> (8UL))) << 2UL))));

  return (uint32_t)(((*preg) & ((0xFFFFUL << (0U))))

                   );
}


















 
static __inline uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
{
  const volatile uint32_t *preg = ((volatile uint32_t *)((uint32_t) ((uint32_t)(&(ADCx->JDR1)) + ((((Rank & ((0x00000000UL) | (0x00000100UL) | (0x00000200UL) | (0x00000300UL))) >> (8UL))) << 2UL))));

  return (uint16_t)(((*preg) & ((0xFFFFUL << (0U))))

                   );
}


















 
static __inline uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
{
  const volatile uint32_t *preg = ((volatile uint32_t *)((uint32_t) ((uint32_t)(&(ADCx->JDR1)) + ((((Rank & ((0x00000000UL) | (0x00000100UL) | (0x00000200UL) | (0x00000300UL))) >> (8UL))) << 2UL))));

  return (uint16_t)(((*preg) & ((0xFFFFUL << (0U))))

                   );
}


















 
static __inline uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
{
  const volatile uint32_t *preg = ((volatile uint32_t *)((uint32_t) ((uint32_t)(&(ADCx->JDR1)) + ((((Rank & ((0x00000000UL) | (0x00000100UL) | (0x00000200UL) | (0x00000300UL))) >> (8UL))) << 2UL))));

  return (uint8_t)(((*preg) & ((0xFFFFUL << (0U))))

                  );
}


















 
static __inline uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
{
  const volatile uint32_t *preg = ((volatile uint32_t *)((uint32_t) ((uint32_t)(&(ADCx->JDR1)) + ((((Rank & ((0x00000000UL) | (0x00000100UL) | (0x00000200UL) | (0x00000300UL))) >> (8UL))) << 2UL))));

  return (uint8_t)(((*preg) & ((0xFFFFUL << (0U))))

                  );
}



 



 









 
static __inline uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
{
  return ((((ADCx->ISR) & ((0x1UL << (0U)))) == ((0x1UL << (0U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
{
  return ((((ADCx->ISR) & ((0x1UL << (2U)))) == ((0x1UL << (2U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
{
  return ((((ADCx->ISR) & ((0x1UL << (3U)))) == ((0x1UL << (3U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
{
  return ((((ADCx->ISR) & ((0x1UL << (4U)))) == ((0x1UL << (4U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
{
  return ((((ADCx->ISR) & ((0x1UL << (1U)))) == ((0x1UL << (1U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)
{
  return ((((ADCx->ISR) & ((0x1UL << (5U)))) == ((0x1UL << (5U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
{
  return ((((ADCx->ISR) & ((0x1UL << (6U)))) == ((0x1UL << (6U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)
{
  return ((((ADCx->ISR) & ((0x1UL << (10U)))) == ((0x1UL << (10U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
{
  return ((((ADCx->ISR) & ((0x1UL << (7U)))) == ((0x1UL << (7U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
{
  return ((((ADCx->ISR) & ((0x1UL << (8U)))) == ((0x1UL << (8U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
{
  return ((((ADCx->ISR) & ((0x1UL << (9U)))) == ((0x1UL << (9U)))) ? 1UL : 0UL);
}









 
static __inline void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
{
  ((ADCx->ISR) = ((0x1UL << (0U))));
}






 
static __inline void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
{
  ((ADCx->ISR) = ((0x1UL << (2U))));
}






 
static __inline void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
{
  ((ADCx->ISR) = ((0x1UL << (3U))));
}






 
static __inline void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
{
  ((ADCx->ISR) = ((0x1UL << (4U))));
}






 
static __inline void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
{
  ((ADCx->ISR) = ((0x1UL << (1U))));
}






 
static __inline void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
{
  ((ADCx->ISR) = ((0x1UL << (5U))));
}






 
static __inline void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
{
  ((ADCx->ISR) = ((0x1UL << (6U))));
}






 
static __inline void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
{
  ((ADCx->ISR) = ((0x1UL << (10U))));
}






 
static __inline void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
{
  ((ADCx->ISR) = ((0x1UL << (7U))));
}






 
static __inline void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
{
  ((ADCx->ISR) = ((0x1UL << (8U))));
}






 
static __inline void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
{
  ((ADCx->ISR) = ((0x1UL << (9U))));
}








 
static __inline uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
{
  return ((((ADCxy_COMMON->CSR) & ((0x1UL << (0U)))) == ((0x1UL << (0U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
{
  return ((((ADCxy_COMMON->CSR) & ((0x1UL << (16U)))) == ((0x1UL << (16U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
{
  return ((((ADCxy_COMMON->CSR) & ((0x1UL << (18U)))) == ((0x1UL << (18U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
{
  return ((((ADCxy_COMMON->CSR) & ((0x1UL << (18U)))) == ((0x1UL << (18U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
{
  return ((((ADCxy_COMMON->CSR) & ((0x1UL << (3U)))) == ((0x1UL << (3U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
{
  return ((((ADCxy_COMMON->CSR) & ((0x1UL << (19U)))) == ((0x1UL << (19U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
{
  return ((((ADCxy_COMMON->CSR) & ((0x1UL << (4U)))) == ((0x1UL << (4U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
{
  return ((((ADCxy_COMMON->CSR) & ((0x1UL << (20U)))) == ((0x1UL << (20U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
{
  return ((((ADCxy_COMMON->CSR) & ((0x1UL << (1U)))) == ((0x1UL << (1U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
{
  return ((((ADCxy_COMMON->CSR) & ((0x1UL << (17U)))) == ((0x1UL << (17U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
{
  return ((((ADCxy_COMMON->CSR) & ((0x1UL << (5U)))) == ((0x1UL << (5U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
{
  return ((((ADCxy_COMMON->CSR) & ((0x1UL << (21U)))) == ((0x1UL << (21U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
{
  return ((((ADCxy_COMMON->CSR) & ((0x1UL << (6U)))) == ((0x1UL << (6U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
{
  return ((((ADCxy_COMMON->CSR) & ((0x1UL << (22U)))) == ((0x1UL << (22U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
{
  return ((((ADCxy_COMMON->CSR) & ((0x1UL << (10U)))) == ((0x1UL << (10U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
{
  return ((((ADCxy_COMMON->CSR) & ((0x1UL << (26U)))) == ((0x1UL << (26U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
{
  return ((((ADCxy_COMMON->CSR) & ((0x1UL << (7U)))) == ((0x1UL << (7U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
{
  return ((((ADCxy_COMMON->CSR) & ((0x1UL << (23U)))) == ((0x1UL << (23U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
{
  return ((((ADCxy_COMMON->CSR) & ((0x1UL << (8U)))) == ((0x1UL << (8U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
{
  return ((((ADCxy_COMMON->CSR) & ((0x1UL << (24U)))) == ((0x1UL << (24U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
{
  return ((((ADCxy_COMMON->CSR) & ((0x1UL << (9U)))) == ((0x1UL << (9U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
{
  return ((((ADCxy_COMMON->CSR) & ((0x1UL << (25U)))) == ((0x1UL << (25U)))) ? 1UL : 0UL);
}




 



 






 
static __inline void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
{
  ((ADCx->IER) |= ((0x1UL << (0U))));
}






 
static __inline void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
{
  ((ADCx->IER) |= ((0x1UL << (2U))));
}






 
static __inline void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
{
  ((ADCx->IER) |= ((0x1UL << (3U))));
}






 
static __inline void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
{
  ((ADCx->IER) |= ((0x1UL << (4U))));
}






 
static __inline void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
{
  ((ADCx->IER) |= ((0x1UL << (1U))));
}






 
static __inline void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
{
  ((ADCx->IER) |= ((0x1UL << (5U))));
}






 
static __inline void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
{
  ((ADCx->IER) |= ((0x1UL << (6U))));
}






 
static __inline void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
{
  ((ADCx->IER) |= ((0x1UL << (10U))));
}






 
static __inline void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
{
  ((ADCx->IER) |= ((0x1UL << (7U))));
}






 
static __inline void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
{
  ((ADCx->IER) |= ((0x1UL << (8U))));
}






 
static __inline void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
{
  ((ADCx->IER) |= ((0x1UL << (9U))));
}






 
static __inline void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
{
  ((ADCx->IER) &= ~((0x1UL << (0U))));
}






 
static __inline void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
{
  ((ADCx->IER) &= ~((0x1UL << (2U))));
}






 
static __inline void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
{
  ((ADCx->IER) &= ~((0x1UL << (3U))));
}






 
static __inline void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
{
  ((ADCx->IER) &= ~((0x1UL << (4U))));
}






 
static __inline void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
{
  ((ADCx->IER) &= ~((0x1UL << (1U))));
}






 
static __inline void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
{
  ((ADCx->IER) &= ~((0x1UL << (5U))));
}






 
static __inline void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
{
  ((ADCx->IER) &= ~((0x1UL << (6U))));
}






 
static __inline void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
{
  ((ADCx->IER) &= ~((0x1UL << (10U))));
}






 
static __inline void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
{
  ((ADCx->IER) &= ~((0x1UL << (7U))));
}






 
static __inline void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
{
  ((ADCx->IER) &= ~((0x1UL << (8U))));
}






 
static __inline void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
{
  ((ADCx->IER) &= ~((0x1UL << (9U))));
}







 
static __inline uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
{
  return ((((ADCx->IER) & ((0x1UL << (0U)))) == ((0x1UL << (0U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
{
  return ((((ADCx->IER) & ((0x1UL << (2U)))) == ((0x1UL << (2U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
{
  return ((((ADCx->IER) & ((0x1UL << (3U)))) == ((0x1UL << (3U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
{
  return ((((ADCx->IER) & ((0x1UL << (4U)))) == ((0x1UL << (4U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
{
  return ((((ADCx->IER) & ((0x1UL << (1U)))) == ((0x1UL << (1U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)
{
  return ((((ADCx->IER) & ((0x1UL << (5U)))) == ((0x1UL << (5U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
{
  return ((((ADCx->IER) & ((0x1UL << (6U)))) == ((0x1UL << (6U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)
{
  return ((((ADCx->IER) & ((0x1UL << (10U)))) == ((0x1UL << (10U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
{
  return ((((ADCx->IER) & ((0x1UL << (7U)))) == ((0x1UL << (7U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
{
  return ((((ADCx->IER) & ((0x1UL << (8U)))) == ((0x1UL << (8U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
{
  return ((((ADCx->IER) & ((0x1UL << (9U)))) == ((0x1UL << (9U)))) ? 1UL : 0UL);
}



 




 

 
ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
void        LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);

 
 
ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);

 
ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
void        LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);

 
ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
void        LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);

 
ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
void        LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);



 




 



 





 





#line 33 "../Core/Inc/main.h"
#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cordic.h"
















 

 







 
#line 29 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cordic.h"



 





 

 

 

 

 

 


 




 



 




 



 



 
#line 84 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cordic.h"


 



 
#line 112 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cordic.h"


 



 
#line 127 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cordic.h"


 



 
#line 140 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cordic.h"


 



 
#line 153 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cordic.h"


 



 




 



 




 



 




 



 

 


 



 







 







 



 



 


 



 



 






































































 
static __inline void LL_CORDIC_Config(CORDIC_TypeDef *CORDICx, uint32_t Function, uint32_t Precision, uint32_t Scale,
                                      uint32_t NbWrite, uint32_t NbRead, uint32_t InSize, uint32_t OutSize)
{
  (((CORDICx->CSR)) = ((((((CORDICx->CSR))) & (~((0xFUL << (0U)) | (0xFUL << (4U)) | (0x7UL << (8U)) | (0x1UL << (20U)) | (0x1UL << (19U)) | (0x1UL << (22U)) | (0x1UL << (21U))))) | (Function | Precision | Scale | NbWrite | NbRead | InSize | OutSize))));




}

















 
static __inline void LL_CORDIC_SetFunction(CORDIC_TypeDef *CORDICx, uint32_t Function)
{
  (((CORDICx->CSR)) = ((((((CORDICx->CSR))) & (~((0xFUL << (0U))))) | (Function))));
}
















 
static __inline uint32_t LL_CORDIC_GetFunction(CORDIC_TypeDef *CORDICx)
{
  return (uint32_t)(((CORDICx->CSR) & ((0xFUL << (0U)))));
}






















 
static __inline void LL_CORDIC_SetPrecision(CORDIC_TypeDef *CORDICx, uint32_t Precision)
{
  (((CORDICx->CSR)) = ((((((CORDICx->CSR))) & (~((0xFUL << (4U))))) | (Precision))));
}





















 
static __inline uint32_t LL_CORDIC_GetPrecision(CORDIC_TypeDef *CORDICx)
{
  return (uint32_t)(((CORDICx->CSR) & ((0xFUL << (4U)))));
}















 
static __inline void LL_CORDIC_SetScale(CORDIC_TypeDef *CORDICx, uint32_t Scale)
{
  (((CORDICx->CSR)) = ((((((CORDICx->CSR))) & (~((0x7UL << (8U))))) | (Scale))));
}














 
static __inline uint32_t LL_CORDIC_GetScale(CORDIC_TypeDef *CORDICx)
{
  return (uint32_t)(((CORDICx->CSR) & ((0x7UL << (8U)))));
}









 
static __inline void LL_CORDIC_SetNbWrite(CORDIC_TypeDef *CORDICx, uint32_t NbWrite)
{
  (((CORDICx->CSR)) = ((((((CORDICx->CSR))) & (~((0x1UL << (20U))))) | (NbWrite))));
}








 
static __inline uint32_t LL_CORDIC_GetNbWrite(CORDIC_TypeDef *CORDICx)
{
  return (uint32_t)(((CORDICx->CSR) & ((0x1UL << (20U)))));
}









 
static __inline void LL_CORDIC_SetNbRead(CORDIC_TypeDef *CORDICx, uint32_t NbRead)
{
  (((CORDICx->CSR)) = ((((((CORDICx->CSR))) & (~((0x1UL << (19U))))) | (NbRead))));
}








 
static __inline uint32_t LL_CORDIC_GetNbRead(CORDIC_TypeDef *CORDICx)
{
  return (uint32_t)(((CORDICx->CSR) & ((0x1UL << (19U)))));
}









 
static __inline void LL_CORDIC_SetInSize(CORDIC_TypeDef *CORDICx, uint32_t InSize)
{
  (((CORDICx->CSR)) = ((((((CORDICx->CSR))) & (~((0x1UL << (22U))))) | (InSize))));
}








 
static __inline uint32_t LL_CORDIC_GetInSize(CORDIC_TypeDef *CORDICx)
{
  return (uint32_t)(((CORDICx->CSR) & ((0x1UL << (22U)))));
}









 
static __inline void LL_CORDIC_SetOutSize(CORDIC_TypeDef *CORDICx, uint32_t OutSize)
{
  (((CORDICx->CSR)) = ((((((CORDICx->CSR))) & (~((0x1UL << (21U))))) | (OutSize))));
}








 
static __inline uint32_t LL_CORDIC_GetOutSize(CORDIC_TypeDef *CORDICx)
{
  return (uint32_t)(((CORDICx->CSR) & ((0x1UL << (21U)))));
}



 



 






 
static __inline void LL_CORDIC_EnableIT(CORDIC_TypeDef *CORDICx)
{
  ((CORDICx->CSR) |= ((0x1UL << (16U))));
}






 
static __inline void LL_CORDIC_DisableIT(CORDIC_TypeDef *CORDICx)
{
  ((CORDICx->CSR) &= ~((0x1UL << (16U))));
}






 
static __inline uint32_t LL_CORDIC_IsEnabledIT(CORDIC_TypeDef *CORDICx)
{
  return ((((CORDICx->CSR) & ((0x1UL << (16U)))) == ((0x1UL << (16U)))) ? 1U : 0U);
}



 



 






 
static __inline void LL_CORDIC_EnableDMAReq_RD(CORDIC_TypeDef *CORDICx)
{
  ((CORDICx->CSR) |= ((0x1UL << (17U))));
}






 
static __inline void LL_CORDIC_DisableDMAReq_RD(CORDIC_TypeDef *CORDICx)
{
  ((CORDICx->CSR) &= ~((0x1UL << (17U))));
}






 
static __inline uint32_t LL_CORDIC_IsEnabledDMAReq_RD(CORDIC_TypeDef *CORDICx)
{
  return ((((CORDICx->CSR) & ((0x1UL << (17U)))) == ((0x1UL << (17U)))) ? 1U : 0U);
}






 
static __inline void LL_CORDIC_EnableDMAReq_WR(CORDIC_TypeDef *CORDICx)
{
  ((CORDICx->CSR) |= ((0x1UL << (18U))));
}






 
static __inline void LL_CORDIC_DisableDMAReq_WR(CORDIC_TypeDef *CORDICx)
{
  ((CORDICx->CSR) &= ~((0x1UL << (18U))));
}






 
static __inline uint32_t LL_CORDIC_IsEnabledDMAReq_WR(CORDIC_TypeDef *CORDICx)
{
  return ((((CORDICx->CSR) & ((0x1UL << (18U)))) == ((0x1UL << (18U)))) ? 1U : 0U);
}










 
static __inline uint32_t LL_CORDIC_DMA_GetRegAddr(CORDIC_TypeDef *CORDICx, uint32_t Direction)
{
  uint32_t data_reg_addr;

  if (Direction == (0x00000001U))
  {
     
    data_reg_addr = (uint32_t) &(CORDICx->RDATA);
  }
  else
  {
     
    data_reg_addr = (uint32_t) &(CORDICx->WDATA);
  }

  return data_reg_addr;
}



 



 






 
static __inline uint32_t LL_CORDIC_IsActiveFlag_RRDY(CORDIC_TypeDef *CORDICx)
{
  return ((((CORDICx->CSR) & ((0x1UL << (31U)))) == ((0x1UL << (31U)))) ? 1U : 0U);
}



 



 







 
static __inline void LL_CORDIC_WriteData(CORDIC_TypeDef *CORDICx, uint32_t InData)
{
  ((CORDICx->WDATA) = (InData));
}






 
static __inline uint32_t LL_CORDIC_ReadData(CORDIC_TypeDef *CORDICx)
{
  return (uint32_t)(((CORDICx->RDATA)));
}



 






 
ErrorStatus LL_CORDIC_DeInit(CORDIC_TypeDef *CORDICx);



 




 



 





 





#line 34 "../Core/Inc/main.h"
#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dma.h"
















 

 







 
#line 29 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dma.h"
#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dmamux.h"
















 

 







 
#line 29 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dmamux.h"



 





 

 
 
 


 
 


 



 

 


 



 

 
 


 



 
#line 93 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dmamux.h"


 




 
#line 121 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dmamux.h"


 




 




 



 
#line 254 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dmamux.h"



 



 
#line 278 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dmamux.h"


 



 






 



 
#line 317 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dmamux.h"


 



 






 



 






 



 
#line 367 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dmamux.h"


 



 

 


 


 






 







 



 



 

 


 



 














































































































































 
static __inline void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
{
  (void)(DMAMUXx);
  ((((((DMAMUX_Channel_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL))) + Channel)->CCR)) = (((((((((DMAMUX_Channel_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL))) + Channel)->CCR))) & (~((0xFFUL << (0U))))) | (Request))));
}
















































































































































 
static __inline uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
  (void)(DMAMUXx);
  return (uint32_t)((((((DMAMUX_Channel_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL))) + Channel)->CCR) & ((0xFFUL << (0U)))));
}
























 
static __inline void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
{
  (void)(DMAMUXx);
  ((((((DMAMUX_Channel_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL))) + Channel)->CCR)) = (((((((((DMAMUX_Channel_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL))) + Channel)->CCR))) & (~((0x1FUL << (19U))))) | (((RequestNb - 1U) << (19U))))));
}























 
static __inline uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
  (void)(DMAMUXx);
  return (uint32_t)((((((((DMAMUX_Channel_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL))) + Channel)->CCR) & ((0x1FUL << (19U))))) >> (19U)) + 1U);
}




























 
static __inline void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
{
  (void)(DMAMUXx);
  ((((((DMAMUX_Channel_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL))) + Channel)->CCR)) = (((((((((DMAMUX_Channel_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL))) + Channel)->CCR))) & (~((0x3UL << (17U))))) | (Polarity))));
}



























 
static __inline uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
  (void)(DMAMUXx);
  return (uint32_t)((((((DMAMUX_Channel_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL))) + Channel)->CCR) & ((0x3UL << (17U)))));
}























 
static __inline void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
  (void)(DMAMUXx);
  (((((DMAMUX_Channel_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL))) + Channel)->CCR) |= ((0x1UL << (9U))));
}























 
static __inline void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
  (void)(DMAMUXx);
  (((((DMAMUX_Channel_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL))) + Channel)->CCR) &= ~((0x1UL << (9U))));
}























 
static __inline uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
  (void)(DMAMUXx);
  return (((((((DMAMUX_Channel_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL))) + Channel)->CCR) & ((0x1UL << (9U)))) == ((0x1UL << (9U))))? 1UL : 0UL);
}























 
static __inline void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
  (void)(DMAMUXx);
  (((((DMAMUX_Channel_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL))) + Channel)->CCR) |= ((0x1UL << (16U))));
}























 
static __inline void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
  (void)(DMAMUXx);
  (((((DMAMUX_Channel_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL))) + Channel)->CCR) &= ~((0x1UL << (16U))));
}























 
static __inline uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
  (void)(DMAMUXx);
  return (((((((DMAMUX_Channel_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL))) + Channel)->CCR) & ((0x1UL << (16U)))) == ((0x1UL << (16U))))? 1UL : 0UL);
}













































 
static __inline void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
{
  (void)(DMAMUXx);
  ((((((DMAMUX_Channel_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL))) + Channel)->CCR)) = (((((((((DMAMUX_Channel_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL))) + Channel)->CCR))) & (~((0x1FUL << (24U))))) | (SyncID))));
}












































 
static __inline uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
  (void)(DMAMUXx);
  return (uint32_t)((((((DMAMUX_Channel_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL))) + Channel)->CCR) & ((0x1FUL << (24U)))));
}











 
static __inline void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{
  (void)(DMAMUXx);
  ((((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)((DMAMUX_RequestGen_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0100UL)) + (0x00000004U * (RequestGenChannel)))))->RGCR) |= ((0x1UL << (16U))));
}











 
static __inline void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{
  (void)(DMAMUXx);
  ((((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)((DMAMUX_RequestGen_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0100UL)) + (0x00000004U * (RequestGenChannel)))))->RGCR) &= ~((0x1UL << (16U))));
}











 
static __inline uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{
  (void)(DMAMUXx);
  return ((((((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)((DMAMUX_RequestGen_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0100UL)) + (0x00000004U * (RequestGenChannel)))))->RGCR) & ((0x1UL << (16U)))) == ((0x1UL << (16U))))? 1UL : 0UL);
}
















 
static __inline void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
                                                     uint32_t Polarity)
{
  (void)DMAMUXx;
  (((((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)((DMAMUX_RequestGen_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0100UL)) + (0x00000004U * (RequestGenChannel)))))->RGCR)) = ((((((((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)((DMAMUX_RequestGen_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0100UL)) + (0x00000004U * (RequestGenChannel)))))->RGCR))) & (~((0x3UL << (17U))))) | (Polarity))));

}















 
static __inline uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{
  (void)DMAMUXx;
  return (((((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)((DMAMUX_RequestGen_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0100UL)) + (0x00000004U * (RequestGenChannel)))))->RGCR) & ((0x3UL << (17U)))));

}













 
static __inline void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
                                               uint32_t RequestNb)
{
  (void)DMAMUXx;
  (((((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)((DMAMUX_RequestGen_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0100UL)) + (0x00000004U * (RequestGenChannel)))))->RGCR)) = ((((((((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)((DMAMUX_RequestGen_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0100UL)) + (0x00000004U * (RequestGenChannel)))))->RGCR))) & (~((0x1FUL << (19U))))) | ((RequestNb - 1U) << (19U)))));

}











 
static __inline uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{
  (void)DMAMUXx;
  return ((((((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)((DMAMUX_RequestGen_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0100UL)) + (0x00000004U * (RequestGenChannel)))))->RGCR) & ((0x1FUL << (19U)))) >> (19U)) + 1U);

}

































 
static __inline void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
                                                  uint32_t RequestSignalID)
{
  (void)DMAMUXx;
  (((((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)((DMAMUX_RequestGen_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0100UL)) + (0x00000004U * (RequestGenChannel)))))->RGCR)) = ((((((((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)((DMAMUX_RequestGen_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0100UL)) + (0x00000004U * (RequestGenChannel)))))->RGCR))) & (~((0x1FUL << (0U))))) | (RequestSignalID))));

}
































 
static __inline uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{
  (void)DMAMUXx;
  return (((((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)((DMAMUX_RequestGen_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0100UL)) + (0x00000004U * (RequestGenChannel)))))->RGCR) & ((0x1FUL << (0U)))));

}



 



 






 
static __inline uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  return ((((((DMAMUX_ChannelStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0080UL))->CSR) & ((0x1UL << (0U)))) == ((0x1UL << (0U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  return ((((((DMAMUX_ChannelStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0080UL))->CSR) & ((0x1UL << (1U)))) == ((0x1UL << (1U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  return ((((((DMAMUX_ChannelStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0080UL))->CSR) & ((0x1UL << (2U)))) == ((0x1UL << (2U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  return ((((((DMAMUX_ChannelStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0080UL))->CSR) & ((0x1UL << (3U)))) == ((0x1UL << (3U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  return ((((((DMAMUX_ChannelStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0080UL))->CSR) & ((0x1UL << (4U)))) == ((0x1UL << (4U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  return ((((((DMAMUX_ChannelStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0080UL))->CSR) & ((0x1UL << (5U)))) == ((0x1UL << (5U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  return ((((((DMAMUX_ChannelStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0080UL))->CSR) & ((0x1UL << (6U)))) == ((0x1UL << (6U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  return ((((((DMAMUX_ChannelStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0080UL))->CSR) & ((0x1UL << (7U)))) == ((0x1UL << (7U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  return ((((((DMAMUX_ChannelStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0080UL))->CSR) & ((0x1UL << (8U)))) == ((0x1UL << (8U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  return ((((((DMAMUX_ChannelStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0080UL))->CSR) & ((0x1UL << (9U)))) == ((0x1UL << (9U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  return ((((((DMAMUX_ChannelStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0080UL))->CSR) & ((0x1UL << (10U)))) == ((0x1UL << (10U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  return ((((((DMAMUX_ChannelStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0080UL))->CSR) & ((0x1UL << (11U)))) == ((0x1UL << (11U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  return ((((((DMAMUX_ChannelStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0080UL))->CSR) & ((0x1UL << (12U)))) == ((0x1UL << (12U)))) ? 1UL : 0UL);
}








 
static __inline uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  return ((((((DMAMUX_ChannelStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0080UL))->CSR) & ((0x1UL << (13U)))) == ((0x1UL << (13U)))) ? 1UL : 0UL);
}








 
static __inline uint32_t LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  return ((((((DMAMUX_ChannelStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0080UL))->CSR) & ((0x1UL << (14U)))) == ((0x1UL << (14U)))) ? 1UL : 0UL);
}








 
static __inline uint32_t LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  return ((((((DMAMUX_ChannelStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0080UL))->CSR) & ((0x1UL << (15U)))) == ((0x1UL << (15U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  return ((((((DMAMUX_RequestGenStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0140UL))->RGSR) & ((0x1UL << (0U)))) == ((0x1UL << (0U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  return ((((((DMAMUX_RequestGenStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0140UL))->RGSR) & ((0x1UL << (1U)))) == ((0x1UL << (1U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  return ((((((DMAMUX_RequestGenStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0140UL))->RGSR) & ((0x1UL << (2U)))) == ((0x1UL << (2U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  return ((((((DMAMUX_RequestGenStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0140UL))->RGSR) & ((0x1UL << (3U)))) == ((0x1UL << (3U)))) ? 1UL : 0UL);
}






 
static __inline void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  ((((DMAMUX_ChannelStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0080UL))->CFR) |= ((0x1UL << (0U))));
}






 
static __inline void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  ((((DMAMUX_ChannelStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0080UL))->CFR) |= ((0x1UL << (1U))));
}






 
static __inline void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  ((((DMAMUX_ChannelStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0080UL))->CFR) |= ((0x1UL << (2U))));
}






 
static __inline void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  ((((DMAMUX_ChannelStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0080UL))->CFR) |= ((0x1UL << (3U))));
}






 
static __inline void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  ((((DMAMUX_ChannelStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0080UL))->CFR) |= ((0x1UL << (4U))));
}






 
static __inline void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  ((((DMAMUX_ChannelStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0080UL))->CFR) |= ((0x1UL << (5U))));
}






 
static __inline void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  ((((DMAMUX_ChannelStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0080UL))->CFR) |= ((0x1UL << (6U))));
}






 
static __inline void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  ((((DMAMUX_ChannelStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0080UL))->CFR) |= ((0x1UL << (7U))));
}






 
static __inline void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  ((((DMAMUX_ChannelStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0080UL))->CFR) |= ((0x1UL << (8U))));
}






 
static __inline void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  ((((DMAMUX_ChannelStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0080UL))->CFR) |= ((0x1UL << (9U))));
}






 
static __inline void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  ((((DMAMUX_ChannelStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0080UL))->CFR) |= ((0x1UL << (10U))));
}






 
static __inline void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  ((((DMAMUX_ChannelStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0080UL))->CFR) |= ((0x1UL << (11U))));
}







 
static __inline void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  ((((DMAMUX_ChannelStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0080UL))->CFR) |= ((0x1UL << (12U))));
}








 
static __inline void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  ((((DMAMUX_ChannelStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0080UL))->CFR) |= ((0x1UL << (13U))));
}








 
static __inline void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  ((((DMAMUX_ChannelStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0080UL))->CFR) |= ((0x1UL << (14U))));
}








 
static __inline void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  ((((DMAMUX_ChannelStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0080UL))->CFR) |= ((0x1UL << (15U))));
}







 
static __inline void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  ((((DMAMUX_RequestGenStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0140UL))->RGCFR) |= ((0x1UL << (0U))));
}






 
static __inline void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  ((((DMAMUX_RequestGenStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0140UL))->RGCFR) |= ((0x1UL << (1U))));
}






 
static __inline void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  ((((DMAMUX_RequestGenStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0140UL))->RGCFR) |= ((0x1UL << (2U))));
}






 
static __inline void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
{
  (void)DMAMUXx;
  ((((DMAMUX_RequestGenStatus_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0140UL))->RGCFR) |= ((0x1UL << (3U))));
}



 



 























 
static __inline void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
  (void)(DMAMUXx);
  (((((DMAMUX_Channel_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL))) + Channel)->CCR) |= ((0x1UL << (8U))));
}























 
static __inline void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
  (void)(DMAMUXx);
  (((((DMAMUX_Channel_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL))) + Channel)->CCR) &= ~((0x1UL << (8U))));
}























 
static __inline uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
  (void)(DMAMUXx);
  return ((((((((DMAMUX_Channel_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL))) + Channel)->CCR) & ((0x1UL << (8U))))) == ((0x1UL << (8U))))? 1UL : 0UL);
}











 
static __inline void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{
  (void)DMAMUXx;
  ((((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)((DMAMUX_RequestGen_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0100UL)) + (0x00000004U * (RequestGenChannel)))))->RGCR) |= ((0x1UL << (8U))));

}











 
static __inline void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{
  (void)DMAMUXx;
  ((((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)((DMAMUX_RequestGen_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0100UL)) + (0x00000004U * (RequestGenChannel)))))->RGCR) &= ~((0x1UL << (8U))));

}











 
static __inline uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{
  (void)DMAMUXx;
  return ((((((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)((DMAMUX_RequestGen_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL) + 0x0100UL)) + (0x00000004U * (RequestGenChannel)))))->RGCR) & ((0x1UL << (8U)))) == ((0x1UL << (8U)))) ? 1UL : 0UL);

}



 



 



 





 







#line 30 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dma.h"



 





 

 
 


 
 
static const uint8_t CHANNEL_OFFSET_TAB[] =
{
  (uint8_t)(((((0x40000000UL) + 0x00020000UL)) + 0x0008UL) - (((0x40000000UL) + 0x00020000UL))),
  (uint8_t)(((((0x40000000UL) + 0x00020000UL)) + 0x001CUL) - (((0x40000000UL) + 0x00020000UL))),
  (uint8_t)(((((0x40000000UL) + 0x00020000UL)) + 0x0030UL) - (((0x40000000UL) + 0x00020000UL))),
  (uint8_t)(((((0x40000000UL) + 0x00020000UL)) + 0x0044UL) - (((0x40000000UL) + 0x00020000UL))),
  (uint8_t)(((((0x40000000UL) + 0x00020000UL)) + 0x0058UL) - (((0x40000000UL) + 0x00020000UL))),
  (uint8_t)(((((0x40000000UL) + 0x00020000UL)) + 0x006CUL) - (((0x40000000UL) + 0x00020000UL)))

  ,
  (uint8_t)(((((0x40000000UL) + 0x00020000UL)) + 0x0080UL) - (((0x40000000UL) + 0x00020000UL)))


  ,
  (uint8_t)(((((0x40000000UL) + 0x00020000UL)) + 0x0094UL) - (((0x40000000UL) + 0x00020000UL)))

};


 

 


 
 


 



 

 



 


 


 



 
typedef struct
{
  uint32_t PeriphOrM2MSrcAddress;  


 

  uint32_t MemoryOrM2MDstAddress;  


 

  uint32_t Direction;              



 

  uint32_t Mode;                   




 

  uint32_t PeriphOrM2MSrcIncMode;  



 

  uint32_t MemoryOrM2MDstIncMode;  



 

  uint32_t PeriphOrM2MSrcDataSize; 



 

  uint32_t MemoryOrM2MDstDataSize; 



 

  uint32_t NbData;                 




 

  uint32_t PeriphRequest;          


 

  uint32_t Priority;               


 

} LL_DMA_InitTypeDef;


 


 


 



 
#line 212 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dma.h"


 




 
#line 256 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dma.h"


 




 





 



 
#line 289 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dma.h"


 



 





 



 




 



 




 



 




 



 





 



 





 



 






 



 

 


 



 






 







 



 



 




 
#line 408 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dma.h"




 
#line 444 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dma.h"






 
#line 484 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dma.h"



 



 

 


 



 















 
static __inline void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  ((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR) |= ((0x1UL << (0U))));
}
















 
static __inline void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  ((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR) &= ~((0x1UL << (0U))));
}
















 
static __inline uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  return ((((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR) & ((0x1UL << (0U)))) == ((0x1UL << (0U)))) ? 1UL : 0UL);

}































 
static __inline void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  (((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR)) = ((((((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR))) & (~((0x1UL << (4U)) | (0x1UL << (14U)) | (0x1UL << (5U)) | (0x1UL << (6U)) | (0x1UL << (7U)) | (0x3UL << (8U)) | (0x3UL << (10U)) | (0x3UL << (12U))))) | (Configuration))));


}





















 
static __inline void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  (((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR)) = ((((((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR))) & (~((0x1UL << (4U)) | (0x1UL << (14U))))) | (Direction))));

}




















 
static __inline uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  return (((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR) & ((0x1UL << (4U)) | (0x1UL << (14U)))));

}





















 
static __inline void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  (((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR)) = ((((((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR))) & (~((0x1UL << (5U))))) | (Mode))));

}


















 
static __inline uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  return (((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR) & ((0x1UL << (5U)))));

}



















 
static __inline void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  (((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR)) = ((((((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR))) & (~((0x1UL << (6U))))) | (PeriphOrM2MSrcIncMode))));

}


















 
static __inline uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  return (((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR) & ((0x1UL << (6U)))));

}



















 
static __inline void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  (((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR)) = ((((((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR))) & (~((0x1UL << (7U))))) | (MemoryOrM2MDstIncMode))));

}


















 
static __inline uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  return (((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR) & ((0x1UL << (7U)))));

}




















 
static __inline void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  (((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR)) = ((((((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR))) & (~((0x3UL << (8U))))) | (PeriphOrM2MSrcDataSize))));

}



















 
static __inline uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  return (((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR) & ((0x3UL << (8U)))));

}




















 
static __inline void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  (((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR)) = ((((((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR))) & (~((0x3UL << (10U))))) | (MemoryOrM2MDstDataSize))));

}



















 
static __inline uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  return (((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR) & ((0x3UL << (10U)))));

}





















 
static __inline void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  (((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR)) = ((((((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR))) & (~((0x3UL << (12U))))) | (Priority))));

}




















 
static __inline uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  return (((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR) & ((0x3UL << (12U)))));

}



















 
static __inline void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  (((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CNDTR)) = ((((((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CNDTR))) & (~((0xFFFFUL << (0U))))) | (NbData))));

}


















 
static __inline uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  return (((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CNDTR) & ((0xFFFFUL << (0U)))));

}

























 
static __inline void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
                                            uint32_t DstAddress, uint32_t Direction)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;

   
  if (Direction == (0x1UL << (4U)))
  {
    ((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR) = (SrcAddress));
    ((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR) = (DstAddress));
  }
   
  else
  {
    ((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR) = (SrcAddress));
    ((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR) = (DstAddress));
  }
}



















 
static __inline void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  ((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR) = (MemoryAddress));
}



















 
static __inline void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  ((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR) = (PeriphAddress));
}

















 
static __inline uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  return (((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR)));
}

















 
static __inline uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  return (((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR)));
}



















 
static __inline void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  ((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR) = (MemoryAddress));
}



















 
static __inline void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  ((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR) = (MemoryAddress));
}

















 
static __inline uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  return (((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR)));
}

















 
static __inline uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  return (((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR)));
}













































































































































 
static __inline void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
{
  uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)((DMA_TypeDef *) (((0x40000000UL) + 0x00020000UL)))) >> 10U) * 8U);
  ((((((DMAMUX_Channel_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL))) + Channel + dmamux_ccr_offset)->CCR)) = (((((((((DMAMUX_Channel_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL))) + Channel + dmamux_ccr_offset)->CCR))) & (~((0xFFUL << (0U))))) | (PeriphRequest))));
}











































































































































 
static __inline uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
{
  uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)((DMA_TypeDef *) (((0x40000000UL) + 0x00020000UL)))) >> 10U) * 8U);
  return ((((((DMAMUX_Channel_TypeDef *) ((((0x40000000UL) + 0x00020000UL) + 0x0800UL))) + Channel + dmamux_ccr_offset)->CCR) & ((0xFFUL << (0U)))));
}



 



 






 
static __inline uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
{
  return ((((DMAx->ISR) & ((0x1UL << (0U)))) == ((0x1UL << (0U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
{
  return ((((DMAx->ISR) & ((0x1UL << (4U)))) == ((0x1UL << (4U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
{
  return ((((DMAx->ISR) & ((0x1UL << (8U)))) == ((0x1UL << (8U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
{
  return ((((DMAx->ISR) & ((0x1UL << (12U)))) == ((0x1UL << (12U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
{
  return ((((DMAx->ISR) & ((0x1UL << (16U)))) == ((0x1UL << (16U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
{
  return ((((DMAx->ISR) & ((0x1UL << (20U)))) == ((0x1UL << (20U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
{
  return ((((DMAx->ISR) & ((0x1UL << (24U)))) == ((0x1UL << (24U)))) ? 1UL : 0UL);
}








 
static __inline uint32_t LL_DMA_IsActiveFlag_GI8(DMA_TypeDef *DMAx)
{
  return ((((DMAx->ISR) & ((0x1UL << (28U)))) == ((0x1UL << (28U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
{
  return ((((DMAx->ISR) & ((0x1UL << (1U)))) == ((0x1UL << (1U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
{
  return ((((DMAx->ISR) & ((0x1UL << (5U)))) == ((0x1UL << (5U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
{
  return ((((DMAx->ISR) & ((0x1UL << (9U)))) == ((0x1UL << (9U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
{
  return ((((DMAx->ISR) & ((0x1UL << (13U)))) == ((0x1UL << (13U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
{
  return ((((DMAx->ISR) & ((0x1UL << (17U)))) == ((0x1UL << (17U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
{
  return ((((DMAx->ISR) & ((0x1UL << (21U)))) == ((0x1UL << (21U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
{
  return ((((DMAx->ISR) & ((0x1UL << (25U)))) == ((0x1UL << (25U)))) ? 1UL : 0UL);
}








 
static __inline uint32_t LL_DMA_IsActiveFlag_TC8(DMA_TypeDef *DMAx)
{
  return ((((DMAx->ISR) & ((0x1UL << (29U)))) == ((0x1UL << (29U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
{
  return ((((DMAx->ISR) & ((0x1UL << (2U)))) == ((0x1UL << (2U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
{
  return ((((DMAx->ISR) & ((0x1UL << (6U)))) == ((0x1UL << (6U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
{
  return ((((DMAx->ISR) & ((0x1UL << (10U)))) == ((0x1UL << (10U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
{
  return ((((DMAx->ISR) & ((0x1UL << (14U)))) == ((0x1UL << (14U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
{
  return ((((DMAx->ISR) & ((0x1UL << (18U)))) == ((0x1UL << (18U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
{
  return ((((DMAx->ISR) & ((0x1UL << (22U)))) == ((0x1UL << (22U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
{
  return ((((DMAx->ISR) & ((0x1UL << (26U)))) == ((0x1UL << (26U)))) ? 1UL : 0UL);
}








 
static __inline uint32_t LL_DMA_IsActiveFlag_HT8(DMA_TypeDef *DMAx)
{
  return ((((DMAx->ISR) & ((0x1UL << (30U)))) == ((0x1UL << (30U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
{
  return ((((DMAx->ISR) & ((0x1UL << (3U)))) == ((0x1UL << (3U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
{
  return ((((DMAx->ISR) & ((0x1UL << (7U)))) == ((0x1UL << (7U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
{
  return ((((DMAx->ISR) & ((0x1UL << (11U)))) == ((0x1UL << (11U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
{
  return ((((DMAx->ISR) & ((0x1UL << (15U)))) == ((0x1UL << (15U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
{
  return ((((DMAx->ISR) & ((0x1UL << (19U)))) == ((0x1UL << (19U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
{
  return ((((DMAx->ISR) & ((0x1UL << (23U)))) == ((0x1UL << (23U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
{
  return ((((DMAx->ISR) & ((0x1UL << (27U)))) == ((0x1UL << (27U)))) ? 1UL : 0UL);
}








 
static __inline uint32_t LL_DMA_IsActiveFlag_TE8(DMA_TypeDef *DMAx)
{
  return ((((DMAx->ISR) & ((0x1UL << (31U)))) == ((0x1UL << (31U)))) ? 1UL : 0UL);
}











 
static __inline void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
{
  ((DMAx->IFCR) = ((0x1UL << (0U))));
}










 
static __inline void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
{
  ((DMAx->IFCR) = ((0x1UL << (4U))));
}










 
static __inline void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
{
  ((DMAx->IFCR) = ((0x1UL << (8U))));
}










 
static __inline void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
{
  ((DMAx->IFCR) = ((0x1UL << (12U))));
}










 
static __inline void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
{
  ((DMAx->IFCR) = ((0x1UL << (16U))));
}










 
static __inline void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
{
  ((DMAx->IFCR) = ((0x1UL << (20U))));
}











 
static __inline void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
{
  ((DMAx->IFCR) = ((0x1UL << (24U))));
}












 
static __inline void LL_DMA_ClearFlag_GI8(DMA_TypeDef *DMAx)
{
  ((DMAx->IFCR) = ((0x1UL << (28U))));
}







 
static __inline void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
{
  ((DMAx->IFCR) = ((0x1UL << (1U))));
}






 
static __inline void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
{
  ((DMAx->IFCR) = ((0x1UL << (5U))));
}






 
static __inline void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
{
  ((DMAx->IFCR) = ((0x1UL << (9U))));
}






 
static __inline void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
{
  ((DMAx->IFCR) = ((0x1UL << (13U))));
}






 
static __inline void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
{
  ((DMAx->IFCR) = ((0x1UL << (17U))));
}






 
static __inline void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
{
  ((DMAx->IFCR) = ((0x1UL << (21U))));
}







 
static __inline void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
{
  ((DMAx->IFCR) = ((0x1UL << (25U))));
}








 
static __inline void LL_DMA_ClearFlag_TC8(DMA_TypeDef *DMAx)
{
  ((DMAx->IFCR) = ((0x1UL << (29U))));
}







 
static __inline void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
{
  ((DMAx->IFCR) = ((0x1UL << (2U))));
}






 
static __inline void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
{
  ((DMAx->IFCR) = ((0x1UL << (6U))));
}






 
static __inline void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
{
  ((DMAx->IFCR) = ((0x1UL << (10U))));
}






 
static __inline void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
{
  ((DMAx->IFCR) = ((0x1UL << (14U))));
}






 
static __inline void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
{
  ((DMAx->IFCR) = ((0x1UL << (18U))));
}






 
static __inline void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
{
  ((DMAx->IFCR) = ((0x1UL << (22U))));
}







 
static __inline void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
{
  ((DMAx->IFCR) = ((0x1UL << (26U))));
}








 
static __inline void LL_DMA_ClearFlag_HT8(DMA_TypeDef *DMAx)
{
  ((DMAx->IFCR) = ((0x1UL << (30U))));
}







 
static __inline void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
{
  ((DMAx->IFCR) = ((0x1UL << (3U))));
}






 
static __inline void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
{
  ((DMAx->IFCR) = ((0x1UL << (7U))));
}






 
static __inline void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
{
  ((DMAx->IFCR) = ((0x1UL << (11U))));
}






 
static __inline void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
{
  ((DMAx->IFCR) = ((0x1UL << (15U))));
}






 
static __inline void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
{
  ((DMAx->IFCR) = ((0x1UL << (19U))));
}






 
static __inline void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
{
  ((DMAx->IFCR) = ((0x1UL << (23U))));
}







 
static __inline void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
{
  ((DMAx->IFCR) = ((0x1UL << (27U))));
}








 
static __inline void LL_DMA_ClearFlag_TE8(DMA_TypeDef *DMAx)
{
  ((DMAx->IFCR) = ((0x1UL << (31U))));
}




 



 















 
static __inline void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  ((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR) |= ((0x1UL << (1U))));
}
















 
static __inline void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  ((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR) |= ((0x1UL << (2U))));
}
















 
static __inline void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  ((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR) |= ((0x1UL << (3U))));
}
















 
static __inline void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  ((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR) &= ~((0x1UL << (1U))));
}
















 
static __inline void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  ((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR) &= ~((0x1UL << (2U))));
}
















 
static __inline void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  ((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR) &= ~((0x1UL << (3U))));
}
















 
static __inline uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  return ((((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR) & ((0x1UL << (1U)))) == ((0x1UL << (1U)))) ? 1UL : 0UL);

}
















 
static __inline uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  return ((((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR) & ((0x1UL << (2U)))) == ((0x1UL << (2U)))) ? 1UL : 0UL);

}
















 
static __inline uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
{
  uint32_t dma_base_addr = (uint32_t)DMAx;
  return ((((((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR) & ((0x1UL << (3U)))) == ((0x1UL << (3U)))) ? 1UL : 0UL);

}



 




 

uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);



 




 



 





 







#line 35 "../Core/Inc/main.h"
#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_opamp.h"
















 

 







 
#line 29 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_opamp.h"



 





 

 
 

 


 

 
 
 
 
 





 


 


 








 








 


 



 



 
typedef struct
{
  uint32_t PowerMode;                   


 


  uint32_t FunctionalMode;              



 

  uint32_t InputNonInverting;           


 

  uint32_t InputInverting;              



 

} LL_OPAMP_InitTypeDef;



 


 


 



 




 



 
#line 154 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_opamp.h"



 









 
#line 174 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_opamp.h"


 



 
#line 195 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_opamp.h"


 





 
#line 212 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_opamp.h"


 



 
#line 233 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_opamp.h"


 





 
#line 261 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_opamp.h"


 



 
#line 277 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_opamp.h"


 






 







 



 







 



 




 



 
#line 326 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_opamp.h"


 







 

 
 
 
 
 
 
 
 
 



 



 

 


 


 






 







 



 



 

 


 



 















 
static __inline void LL_OPAMP_SetMode(OPAMP_TypeDef *OPAMPx, uint32_t Mode)
{
  (((OPAMPx->CSR)) = ((((((OPAMPx->CSR))) & (~((0x1UL << (11U))))) | (Mode))));
}














 
static __inline uint32_t LL_OPAMP_GetMode(OPAMP_TypeDef *OPAMPx)
{
  return (uint32_t)(((OPAMPx->CSR) & ((0x1UL << (11U)))));
}


















 
static __inline void LL_OPAMP_SetFunctionalMode(OPAMP_TypeDef *OPAMPx, uint32_t FunctionalMode)
{
   
  (((OPAMPx->CSR)) = ((((((OPAMPx->CSR))) & (~((0x10UL << (14U)) | (0x8UL << (14U)) | (0x3UL << (5U)) | (0x1UL << (11U))))) | (FunctionalMode))));
}













 
static __inline uint32_t LL_OPAMP_GetFunctionalMode(OPAMP_TypeDef *OPAMPx)
{
  return (uint32_t)(((OPAMPx->CSR) & ((0x10UL << (14U)) | (0x8UL << (14U)) | (0x3UL << (5U)))));
}















 
static __inline void LL_OPAMP_SetPGAGain(OPAMP_TypeDef *OPAMPx, uint32_t PGAGain)
{
  (((OPAMPx->CSR)) = ((((((OPAMPx->CSR))) & (~((0x4UL << (14U)) | (0x2UL << (14U)) | (0x1UL << (14U))))) | (PGAGain))));
}














 
static __inline uint32_t LL_OPAMP_GetPGAGain(OPAMP_TypeDef *OPAMPx)
{
  return (uint32_t)(((OPAMPx->CSR) & ((0x4UL << (14U)) | (0x2UL << (14U)) | (0x1UL << (14U)))));
}










 
static __inline void LL_OPAMP_SetPowerMode(OPAMP_TypeDef *OPAMPx, uint32_t PowerMode)
{
  (((OPAMPx->CSR)) = ((((((OPAMPx->CSR))) & (~((0x1UL << (7U))))) | (PowerMode))));
}









 
static __inline uint32_t LL_OPAMP_GetPowerMode(OPAMP_TypeDef *OPAMPx)
{
  return (uint32_t)(((OPAMPx->CSR) & ((0x1UL << (7U)))));
}


 



 












 
static __inline void LL_OPAMP_SetInputNonInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting)
{
  (((OPAMPx->CSR)) = ((((((OPAMPx->CSR))) & (~((0x3UL << (2U))))) | (InputNonInverting))));
}











 
static __inline uint32_t LL_OPAMP_GetInputNonInverting(OPAMP_TypeDef *OPAMPx)
{
  return (uint32_t)(((OPAMPx->CSR) & ((0x3UL << (2U)))));
}














 
static __inline void LL_OPAMP_SetInputInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputInverting)
{
   
   
   
  (((OPAMPx->CSR)) = ((((((OPAMPx->CSR))) & (~((~(InputInverting >> 1)) & (0x1UL << (5U))))) | (InputInverting))));
}









 
static __inline uint32_t LL_OPAMP_GetInputInverting(OPAMP_TypeDef *OPAMPx)
{
  uint32_t input_inverting = ((OPAMPx->CSR) & ((0x3UL << (5U))));

   
   
  return (input_inverting & ~((input_inverting >> 1) & (0x1UL << (5U))));
}












 
static __inline void LL_OPAMP_SetInputNonInvertingSecondary(OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting)
{
  (((OPAMPx->TCMR)) = ((((((OPAMPx->TCMR))) & (~((0x3UL << (1U))))) | (InputNonInverting))));
}











 
static __inline uint32_t LL_OPAMP_GetInputNonInvertingSecondary(OPAMP_TypeDef *OPAMPx)
{
  return (uint32_t)(((OPAMPx->TCMR) & ((0x3UL << (1U)))));
}















 
static __inline void LL_OPAMP_SetInputInvertingSecondary(OPAMP_TypeDef *OPAMPx, uint32_t InputInverting)
{
  (((OPAMPx->TCMR)) = ((((((OPAMPx->TCMR))) & (~((0x1UL << (0U))))) | (InputInverting))));
}










 
static __inline uint32_t LL_OPAMP_GetInputInvertingSecondary(OPAMP_TypeDef *OPAMPx)
{
  return (uint32_t)(((OPAMPx->TCMR) & ((0x1UL << (0U)))));
}












 
static __inline void LL_OPAMP_SetInputsMuxMode(OPAMP_TypeDef *OPAMPx, uint32_t InputsMuxMode)
{
  (((OPAMPx->TCMR)) = ((((((OPAMPx->TCMR))) & (~((0x1UL << (3U)) | (0x1UL << (4U)) | (0x1UL << (5U))))) | (InputsMuxMode))));
}











 
static __inline uint32_t LL_OPAMP_GetInputsMuxMode(OPAMP_TypeDef *OPAMPx)
{
  return (uint32_t)(((OPAMPx->TCMR) & ((0x1UL << (3U)) | (0x1UL << (4U)) | (0x1UL << (5U)))));
}










 
static __inline void LL_OPAMP_SetInternalOutput(OPAMP_TypeDef *OPAMPx, uint32_t InternalOutput)
{
  (((OPAMPx->CSR)) = ((((((OPAMPx->CSR))) & (~((0x1UL << (8U))))) | (InternalOutput))));
}








 
static __inline uint32_t LL_OPAMP_GetInternalOutput(OPAMP_TypeDef *OPAMPx)
{
  return ((OPAMPx->CSR) & ((0x1UL << (8U))));
}



 



 









 
static __inline void LL_OPAMP_SetTrimmingMode(OPAMP_TypeDef *OPAMPx, uint32_t TrimmingMode)
{
  (((OPAMPx->CSR)) = ((((((OPAMPx->CSR))) & (~((0x1UL << (4U))))) | (TrimmingMode))));
}








 
static __inline uint32_t LL_OPAMP_GetTrimmingMode(OPAMP_TypeDef *OPAMPx)
{
  return (uint32_t)(((OPAMPx->CSR) & ((0x1UL << (4U)))));
}


















 
static __inline void LL_OPAMP_SetCalibrationSelection(OPAMP_TypeDef *OPAMPx, uint32_t TransistorsDiffPair)
{
   
   
  (((OPAMPx->CSR)) = ((((((OPAMPx->CSR))) & (~((0x3UL << (12U))))) | ((TransistorsDiffPair & ((0x3UL << (12U))))))));
}

















 
static __inline uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx)
{
  uint32_t CalibrationSelection = (uint32_t)(((OPAMPx->CSR) & ((0x3UL << (12U)))));

  return (CalibrationSelection |
          (((CalibrationSelection & (0x2UL << (12U))) == 0UL) ? (0x1FUL << (19U)) : (0x1FUL << (24U))));
}









 
static __inline uint32_t LL_OPAMP_IsCalibrationOutputSet(OPAMP_TypeDef *OPAMPx)
{
  return ((((OPAMPx->CSR) & ((0x1UL << (30U)))) == (0x1UL << (30U))) ? 1UL : 0UL);
}













 
static __inline void LL_OPAMP_SetTrimmingValue(OPAMP_TypeDef *OPAMPx, uint32_t TransistorsDiffPair,
                                               uint32_t TrimmingValue)
{
  (((OPAMPx->CSR)) = ((((((OPAMPx->CSR))) & (~((TransistorsDiffPair & ((0x1FUL << (24U)) | (0x1FUL << (19U))))))) | (TrimmingValue << ((TransistorsDiffPair == (((0x1FUL << (24U)) | (0x2UL << (12U)) | (0x1UL << (12U))))) ? (24U) : (19U))))));


}












 
static __inline uint32_t LL_OPAMP_GetTrimmingValue(OPAMP_TypeDef *OPAMPx, uint32_t TransistorsDiffPair)
{
  return (uint32_t)(((OPAMPx->CSR) & ((TransistorsDiffPair & ((0x1FUL << (24U)) | (0x1FUL << (19U))))))
                    >> ((TransistorsDiffPair == (((0x1FUL << (24U)) | (0x2UL << (12U)) | (0x1UL << (12U))))) ? (24U) : (19U)));
}



 



 








 
static __inline void LL_OPAMP_Enable(OPAMP_TypeDef *OPAMPx)
{
  ((OPAMPx->CSR) |= ((0x1UL << (0U))));
}






 
static __inline void LL_OPAMP_Disable(OPAMP_TypeDef *OPAMPx)
{
  ((OPAMPx->CSR) &= ~((0x1UL << (0U))));
}







 
static __inline uint32_t LL_OPAMP_IsEnabled(OPAMP_TypeDef *OPAMPx)
{
  return ((((OPAMPx->CSR) & ((0x1UL << (0U)))) == ((0x1UL << (0U)))) ? 1UL : 0UL);
}








 
static __inline void LL_OPAMP_Lock(OPAMP_TypeDef *OPAMPx)
{
  ((OPAMPx->CSR) |= ((0x1UL << (31U))));
}









 
static __inline uint32_t LL_OPAMP_IsLocked(OPAMP_TypeDef *OPAMPx)
{
  return ((((OPAMPx->CSR) & ((0x1UL << (31U)))) == ((0x1UL << (31U)))) ? 1UL : 0UL);
}








 
static __inline void LL_OPAMP_LockTimerMux(OPAMP_TypeDef *OPAMPx)
{
  ((OPAMPx->TCMR) |= ((0x1UL << (31U))));
}









 
static __inline uint32_t LL_OPAMP_IsTimerMuxLocked(OPAMP_TypeDef *OPAMPx)
{
  return ((((OPAMPx->TCMR) & ((0x1UL << (31U)))) == ((0x1UL << (31U)))) ? 1UL : 0UL);
}



 




 

ErrorStatus LL_OPAMP_DeInit(OPAMP_TypeDef *OPAMPx);
ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct);
void        LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct);



 




 



 





 







#line 36 "../Core/Inc/main.h"
#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h"















 

 







 
#line 28 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h"



 



 

 
 


 



 

 


 
 
 





 

 



 


 


 



 



 



 
typedef struct
{
  uint32_t SYSCLK_Frequency;         
  uint32_t HCLK_Frequency;           
  uint32_t PCLK1_Frequency;          
  uint32_t PCLK2_Frequency;          
} LL_RCC_ClocksTypeDef;



 



 


 


 






 


























 




 
#line 151 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h"


 




 
#line 174 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h"


 




 
#line 189 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h"


 



 






 



 




 



 





 



 





 



 
#line 245 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h"


 



 







 



 







 



 
#line 284 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h"


 



 







 




 




 




 
#line 326 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h"


 



 
#line 345 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h"


 



 






 



 
#line 377 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h"


 



 






 



 






 



 






 




 





 




 




 



 




 



 
#line 455 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h"


 



 





 




 





 



 
#line 489 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h"


 



 



 



 
#line 510 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h"


 



 



 



 



 



 



 




 





 



 



 



 



 



 






 



 



 



 






 




 





 



 
#line 625 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h"


 



 






 



 
#line 673 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h"


 



 






 



 

 


 



 






 






 



 



 






























 



























































 
































 

















 












 












 




 



 

 


 



 





 
static __inline void LL_RCC_HSE_EnableCSS(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CR) |= ((0x1UL << (19U))));
}





 
static __inline void LL_RCC_HSE_EnableBypass(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CR) |= ((0x1UL << (18U))));
}





 
static __inline void LL_RCC_HSE_DisableBypass(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CR) &= ~((0x1UL << (18U))));
}





 
static __inline void LL_RCC_HSE_Enable(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CR) |= ((0x1UL << (16U))));
}





 
static __inline void LL_RCC_HSE_Disable(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CR) &= ~((0x1UL << (16U))));
}





 
static __inline uint32_t LL_RCC_HSE_IsReady(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CR) & ((0x1UL << (17U)))) == ((0x1UL << (17U)))) ? 1UL : 0UL);
}



 



 






 
static __inline void LL_RCC_HSI_EnableInStopMode(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CR) |= ((0x1UL << (9U))));
}





 
static __inline void LL_RCC_HSI_DisableInStopMode(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CR) &= ~((0x1UL << (9U))));
}





 
static __inline void LL_RCC_HSI_Enable(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CR) |= ((0x1UL << (8U))));
}





 
static __inline void LL_RCC_HSI_Disable(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CR) &= ~((0x1UL << (8U))));
}





 
static __inline uint32_t LL_RCC_HSI_IsReady(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CR) & ((0x1UL << (10U)))) == ((0x1UL << (10U)))) ? 1UL : 0UL);
}







 
static __inline uint32_t LL_RCC_HSI_GetCalibration(void)
{
  return (uint32_t)(((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->ICSCR) & ((0xFFUL << (16U)))) >> (16U));
}









 
static __inline void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
{
  (((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->ICSCR)) = ((((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->ICSCR))) & (~((0x7FUL << (24U))))) | (Value << (24U)))));
}





 
static __inline uint32_t LL_RCC_HSI_GetCalibTrimming(void)
{
  return (uint32_t)(((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->ICSCR) & ((0x7FUL << (24U)))) >> (24U));
}



 



 





 
static __inline void LL_RCC_HSI48_Enable(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CRRCR) |= ((0x1UL << (0U))));
}





 
static __inline void LL_RCC_HSI48_Disable(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CRRCR) &= ~((0x1UL << (0U))));
}





 
static __inline uint32_t LL_RCC_HSI48_IsReady(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CRRCR) & ((0x1UL << (1U)))) == ((0x1UL << (1U)))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_RCC_HSI48_GetCalibration(void)
{
  return (uint32_t)(((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CRRCR) & ((0x1FFUL << (7U)))) >> (7U));
}



 



 





 
static __inline void LL_RCC_LSE_Enable(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->BDCR) |= ((0x1UL << (0U))));
}





 
static __inline void LL_RCC_LSE_Disable(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->BDCR) &= ~((0x1UL << (0U))));
}





 
static __inline void LL_RCC_LSE_EnableBypass(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->BDCR) |= ((0x1UL << (2U))));
}





 
static __inline void LL_RCC_LSE_DisableBypass(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->BDCR) &= ~((0x1UL << (2U))));
}











 
static __inline void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
{
  (((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->BDCR)) = ((((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->BDCR))) & (~((0x3UL << (3U))))) | (LSEDrive))));
}









 
static __inline uint32_t LL_RCC_LSE_GetDriveCapability(void)
{
  return (uint32_t)(((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->BDCR) & ((0x3UL << (3U)))));
}





 
static __inline void LL_RCC_LSE_EnableCSS(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->BDCR) |= ((0x1UL << (5U))));
}







 
static __inline void LL_RCC_LSE_DisableCSS(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->BDCR) &= ~((0x1UL << (5U))));
}





 
static __inline uint32_t LL_RCC_LSE_IsReady(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->BDCR) & ((0x1UL << (1U)))) == ((0x1UL << (1U)))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_RCC_LSE_IsCSSDetected(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->BDCR) & ((0x1UL << (6U)))) == ((0x1UL << (6U)))) ? 1UL : 0UL);
}



 



 





 
static __inline void LL_RCC_LSI_Enable(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CSR) |= ((0x1UL << (0U))));
}





 
static __inline void LL_RCC_LSI_Disable(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CSR) &= ~((0x1UL << (0U))));
}





 
static __inline uint32_t LL_RCC_LSI_IsReady(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CSR) & ((0x1UL << (1U)))) == ((0x1UL << (1U)))) ? 1UL : 0UL);
}



 



 





 
static __inline void LL_RCC_LSCO_Enable(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->BDCR) |= ((0x1UL << (24U))));
}





 
static __inline void LL_RCC_LSCO_Disable(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->BDCR) &= ~((0x1UL << (24U))));
}








 
static __inline void LL_RCC_LSCO_SetSource(uint32_t Source)
{
  (((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->BDCR)) = ((((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->BDCR))) & (~((0x1UL << (25U))))) | (Source))));
}







 
static __inline uint32_t LL_RCC_LSCO_GetSource(void)
{
  return (uint32_t)(((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->BDCR) & ((0x1UL << (25U)))));
}



 



 









 
static __inline void LL_RCC_SetSysClkSource(uint32_t Source)
{
  (((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CFGR)) = ((((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CFGR))) & (~((0x3UL << (0U))))) | (Source))));
}








 
static __inline uint32_t LL_RCC_GetSysClkSource(void)
{
  return (uint32_t)(((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CFGR) & ((0x3UL << (2U)))));
}















 
static __inline void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
{
  (((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CFGR)) = ((((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CFGR))) & (~((0xFUL << (4U))))) | (Prescaler))));
}











 
static __inline void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
{
  (((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CFGR)) = ((((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CFGR))) & (~((0x7UL << (8U))))) | (Prescaler))));
}











 
static __inline void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
{
  (((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CFGR)) = ((((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CFGR))) & (~((0x7UL << (11U))))) | (Prescaler))));
}














 
static __inline uint32_t LL_RCC_GetAHBPrescaler(void)
{
  return (uint32_t)(((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CFGR) & ((0xFUL << (4U)))));
}










 
static __inline uint32_t LL_RCC_GetAPB1Prescaler(void)
{
  return (uint32_t)(((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CFGR) & ((0x7UL << (8U)))));
}










 
static __inline uint32_t LL_RCC_GetAPB2Prescaler(void)
{
  return (uint32_t)(((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CFGR) & ((0x7UL << (11U)))));
}



 



 























 
static __inline void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
{
  (((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CFGR)) = ((((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CFGR))) & (~((0xFUL << (24U)) | (0x7UL << (28U))))) | (MCOxSource | MCOxPrescaler))));
}



 



 


















 
static __inline void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
{
  (((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR)) = ((((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR))) & (~((USARTxSource >> 16U)))) | ((USARTxSource & 0x0000FFFFU)))));
}

















 
static __inline void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
{
  (((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR)) = ((((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR))) & (~((UARTxSource >> 16U)))) | ((UARTxSource & 0x0000FFFFU)))));
}











 
static __inline void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
{
  (((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR)) = ((((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR))) & (~((0x3UL << (10U))))) | (LPUARTxSource))));
}




















 
static __inline void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
{
  volatile uint32_t *reg = (volatile uint32_t *)(uint32_t)((((0x40000000UL) + 0x00020000UL) + 0x1000UL) + 0x88U + (I2CxSource >> 24U));
  (((*reg)) = ((((((*reg))) & (~(3UL << ((I2CxSource & 0x001F0000U) >> 16U)))) | (((I2CxSource & 0x000000FFU) << ((I2CxSource & 0x001F0000U) >> 16U))))));
}










 
static __inline void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
{
  (((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR)) = ((((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR))) & (~((0x3UL << (18U))))) | (LPTIMxSource))));
}












 
static __inline void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
{
  (((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR)) = ((((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR))) & (~((0x3UL << (20U))))) | (SAIxSource))));
}










 
static __inline void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
{
  (((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR)) = ((((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR))) & (~((0x3UL << (22U))))) | (I2SxSource))));
}










 
static __inline void LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource)
{
  (((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR)) = ((((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR))) & (~((0x3UL << (24U))))) | (FDCANxSource))));
}









 
static __inline void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
{
  (((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR)) = ((((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR))) & (~((0x3UL << (26U))))) | (RNGxSource))));
}








 
static __inline void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
{
  (((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR)) = ((((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR))) & (~((0x3UL << (26U))))) | (USBxSource))));
}















 
static __inline void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
{
  (((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR)) = ((((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR))) & (~(3U << ((ADCxSource & 0x001F0000U) >> 16U)))) | (((ADCxSource & 0x000000FFU) << ((ADCxSource & 0x001F0000U) >> 16U))))));
}










 
static __inline void LL_RCC_SetQUADSPIClockSource(uint32_t Source)
{
  (((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR2)) = ((((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR2))) & (~((0x3UL << (20U))))) | (Source))));
}






















 
static __inline uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
{
  return (uint32_t)(((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR) & (USARTx)) | (USARTx << 16U));
}



















 
static __inline uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
{
  return (uint32_t)(((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR) & (UARTx)) | (UARTx << 16U));
}












 
static __inline uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
{
  return (uint32_t)(((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR) & (LPUARTx)));
}


























 
static __inline uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
{
  volatile const uint32_t *reg = (volatile uint32_t *)(uint32_t)((((0x40000000UL) + 0x00020000UL) + 0x1000UL) + 0x88U + (I2Cx >> 24U));
  return (uint32_t)((((*reg) & (3UL << ((I2Cx & 0x001F0000U) >> 16U))) >> ((I2Cx & 0x001F0000U) >> 16U)) | (I2Cx & 0xFFFF0000U));
}











 
static __inline uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
{
  return (uint32_t)(((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR) & (LPTIMx)));
}















 
static __inline uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
{
  return (uint32_t)(((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR) & (SAIx)));
}











 
static __inline uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
{
  return (uint32_t)(((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR) & (I2Sx)));
}












 
static __inline uint32_t LL_RCC_GetFDCANClockSource(uint32_t FDCANx)
{
  return (uint32_t)(((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR) & (FDCANx)));
}










 
static __inline uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
{
  return (uint32_t)(((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR) & (RNGx)));
}









 
static __inline uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
{
  return (uint32_t)(((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR) & (USBx)));
}
















 
static __inline uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
{
  return (uint32_t)((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR) & (3UL << ((ADCx & 0x001F0000U) >> 16U))) >> ((ADCx & 0x001F0000U) >> 16U)) | (ADCx & 0xFFFF0000U));
}











 
static __inline uint32_t LL_RCC_GetQUADSPIClockSource(uint32_t QUADSPIx)
{
  return (uint32_t)(((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CCIPR2) & (QUADSPIx)));
}



 



 













 
static __inline void LL_RCC_SetRTCClockSource(uint32_t Source)
{
  (((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->BDCR)) = ((((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->BDCR))) & (~((0x3UL << (8U))))) | (Source))));
}









 
static __inline uint32_t LL_RCC_GetRTCClockSource(void)
{
  return (uint32_t)(((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->BDCR) & ((0x3UL << (8U)))));
}





 
static __inline void LL_RCC_EnableRTC(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->BDCR) |= ((0x1UL << (15U))));
}





 
static __inline void LL_RCC_DisableRTC(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->BDCR) &= ~((0x1UL << (15U))));
}





 
static __inline uint32_t LL_RCC_IsEnabledRTC(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->BDCR) & ((0x1UL << (15U)))) == ((0x1UL << (15U)))) ? 1UL : 0UL);
}





 
static __inline void LL_RCC_ForceBackupDomainReset(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->BDCR) |= ((0x1UL << (16U))));
}





 
static __inline void LL_RCC_ReleaseBackupDomainReset(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->BDCR) &= ~((0x1UL << (16U))));
}



 




 





 
static __inline void LL_RCC_PLL_Enable(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CR) |= ((0x1UL << (24U))));
}






 
static __inline void LL_RCC_PLL_Disable(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CR) &= ~((0x1UL << (24U))));
}





 
static __inline uint32_t LL_RCC_PLL_IsReady(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CR) & ((0x1UL << (25U)))) == ((0x1UL << (25U)))) ? 1UL : 0UL);
}






































 
static __inline void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
{
  (((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->PLLCFGR)) = ((((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->PLLCFGR))) & (~((0x3UL << (0U)) | (0xFUL << (4U)) | (0x7FUL << (8U)) | (0x3UL << (25U))))) | (Source | PLLM | (PLLN << (8U)) | PLLR))));

}
































































 
static __inline void LL_RCC_PLL_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
{
  (((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->PLLCFGR)) = ((((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->PLLCFGR))) & (~((0x3UL << (0U)) | (0xFUL << (4U)) | (0x7FUL << (8U)) | (0x1FUL << (27U))))) | (Source | PLLM | (PLLN << (8U)) | PLLP))));

}







































 
static __inline void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
{
  (((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->PLLCFGR)) = ((((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->PLLCFGR))) & (~((0x3UL << (0U)) | (0xFUL << (4U)) | (0x7FUL << (8U)) | (0x3UL << (21U))))) | (Source | PLLM | (PLLN << (8U)) | PLLQ))));

}









 
static __inline void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
{
  (((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->PLLCFGR)) = ((((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->PLLCFGR))) & (~((0x3UL << (0U))))) | (PLLSource))));
}








 
static __inline uint32_t LL_RCC_PLL_GetMainSource(void)
{
  return (uint32_t)(((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->PLLCFGR) & ((0x3UL << (0U)))));
}





 
static __inline uint32_t LL_RCC_PLL_GetN(void)
{
  return (uint32_t)(((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->PLLCFGR) & ((0x7FUL << (8U)))) >>  (8U));
}





































 
static __inline uint32_t LL_RCC_PLL_GetP(void)
{
  return (uint32_t) ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->PLLCFGR) & ((0x1FUL << (27U)))) != 0U) ? ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->PLLCFGR) & ((0x1FUL << (27U)))) : ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->PLLCFGR) & ((0x1UL << (17U)))) == (0x1UL << (17U))) ? ((0x10UL << (27U))|(0x01UL << (27U))) : ((0x04UL << (27U))|(0x02UL << (27U))|(0x01UL << (27U)))) );
}










 
static __inline uint32_t LL_RCC_PLL_GetQ(void)
{
  return (uint32_t)(((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->PLLCFGR) & ((0x3UL << (21U)))));
}










 
static __inline uint32_t LL_RCC_PLL_GetR(void)
{
  return (uint32_t)(((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->PLLCFGR) & ((0x3UL << (25U)))));
}





















 
static __inline uint32_t LL_RCC_PLL_GetDivider(void)
{
  return (uint32_t)(((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->PLLCFGR) & ((0xFUL << (4U)))));
}





 
static __inline void LL_RCC_PLL_EnableDomain_ADC(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->PLLCFGR) |= ((0x1UL << (16U))));
}









 
static __inline void LL_RCC_PLL_DisableDomain_ADC(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->PLLCFGR) &= ~((0x1UL << (16U))));
}





 
static __inline uint32_t LL_RCC_PLL_IsEnabledDomain_ADC(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->PLLCFGR) & ((0x1UL << (16U)))) == ((0x1UL << (16U)))) ? 1UL : 0UL);
}





 
static __inline void LL_RCC_PLL_EnableDomain_48M(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->PLLCFGR) |= ((0x1UL << (20U))));
}









 
static __inline void LL_RCC_PLL_DisableDomain_48M(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->PLLCFGR) &= ~((0x1UL << (20U))));
}





 
static __inline uint32_t LL_RCC_PLL_IsEnabledDomain_48M(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->PLLCFGR) & ((0x1UL << (20U)))) == ((0x1UL << (20U)))) ? 1UL : 0UL);
}





 
static __inline void LL_RCC_PLL_EnableDomain_SYS(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->PLLCFGR) |= ((0x1UL << (24U))));
}









 
static __inline void LL_RCC_PLL_DisableDomain_SYS(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->PLLCFGR) &= ~((0x1UL << (24U))));
}





 
static __inline uint32_t LL_RCC_PLL_IsEnabledDomain_SYS(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->PLLCFGR) & ((0x1UL << (24U)))) == ((0x1UL << (24U)))) ? 1UL : 0UL);
}



 



 





 
static __inline void LL_RCC_ClearFlag_LSIRDY(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CICR) |= ((0x1UL << (0U))));
}





 
static __inline void LL_RCC_ClearFlag_LSERDY(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CICR) |= ((0x1UL << (1U))));
}





 
static __inline void LL_RCC_ClearFlag_HSIRDY(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CICR) |= ((0x1UL << (3U))));
}





 
static __inline void LL_RCC_ClearFlag_HSERDY(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CICR) |= ((0x1UL << (4U))));
}





 
static __inline void LL_RCC_ClearFlag_PLLRDY(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CICR) |= ((0x1UL << (5U))));
}





 
static __inline void LL_RCC_ClearFlag_HSI48RDY(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CICR) |= ((0x1UL << (10U))));
}





 
static __inline void LL_RCC_ClearFlag_HSECSS(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CICR) |= ((0x1UL << (8U))));
}





 
static __inline void LL_RCC_ClearFlag_LSECSS(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CICR) |= ((0x1UL << (9U))));
}





 
static __inline uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CIFR) & ((0x1UL << (0U)))) == ((0x1UL << (0U)))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CIFR) & ((0x1UL << (1U)))) == ((0x1UL << (1U)))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CIFR) & ((0x1UL << (3U)))) == ((0x1UL << (3U)))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CIFR) & ((0x1UL << (4U)))) == ((0x1UL << (4U)))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CIFR) & ((0x1UL << (5U)))) == ((0x1UL << (5U)))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CIFR) & ((0x1UL << (10U)))) == ((0x1UL << (10U)))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CIFR) & ((0x1UL << (8U)))) == ((0x1UL << (8U)))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CIFR) & ((0x1UL << (9U)))) == ((0x1UL << (9U)))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CSR) & ((0x1UL << (29U)))) == ((0x1UL << (29U)))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CSR) & ((0x1UL << (31U)))) == ((0x1UL << (31U)))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CSR) & ((0x1UL << (25U)))) == ((0x1UL << (25U)))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_RCC_IsActiveFlag_PINRST(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CSR) & ((0x1UL << (26U)))) == ((0x1UL << (26U)))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CSR) & ((0x1UL << (28U)))) == ((0x1UL << (28U)))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CSR) & ((0x1UL << (30U)))) == ((0x1UL << (30U)))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_RCC_IsActiveFlag_BORRST(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CSR) & ((0x1UL << (27U)))) == ((0x1UL << (27U)))) ? 1UL : 0UL);
}





 
static __inline void LL_RCC_ClearResetFlags(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CSR) |= ((0x1UL << (23U))));
}



 



 





 
static __inline void LL_RCC_EnableIT_LSIRDY(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CIER) |= ((0x1UL << (0U))));
}





 
static __inline void LL_RCC_EnableIT_LSERDY(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CIER) |= ((0x1UL << (1U))));
}





 
static __inline void LL_RCC_EnableIT_HSIRDY(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CIER) |= ((0x1UL << (3U))));
}





 
static __inline void LL_RCC_EnableIT_HSERDY(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CIER) |= ((0x1UL << (4U))));
}





 
static __inline void LL_RCC_EnableIT_PLLRDY(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CIER) |= ((0x1UL << (5U))));
}





 
static __inline void LL_RCC_EnableIT_HSI48RDY(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CIER) |= ((0x1UL << (10U))));
}





 
static __inline void LL_RCC_EnableIT_LSECSS(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CIER) |= ((0x1UL << (9U))));
}





 
static __inline void LL_RCC_DisableIT_LSIRDY(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CIER) &= ~((0x1UL << (0U))));
}





 
static __inline void LL_RCC_DisableIT_LSERDY(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CIER) &= ~((0x1UL << (1U))));
}





 
static __inline void LL_RCC_DisableIT_HSIRDY(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CIER) &= ~((0x1UL << (3U))));
}





 
static __inline void LL_RCC_DisableIT_HSERDY(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CIER) &= ~((0x1UL << (4U))));
}





 
static __inline void LL_RCC_DisableIT_PLLRDY(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CIER) &= ~((0x1UL << (5U))));
}





 
static __inline void LL_RCC_DisableIT_HSI48RDY(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CIER) &= ~((0x1UL << (10U))));
}





 
static __inline void LL_RCC_DisableIT_LSECSS(void)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CIER) &= ~((0x1UL << (9U))));
}





 
static __inline uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CIER) & ((0x1UL << (0U)))) == ((0x1UL << (0U)))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CIER) & ((0x1UL << (1U)))) == ((0x1UL << (1U)))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CIER) & ((0x1UL << (3U)))) == ((0x1UL << (3U)))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CIER) & ((0x1UL << (4U)))) == ((0x1UL << (4U)))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CIER) & ((0x1UL << (5U)))) == ((0x1UL << (5U)))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CIER) & ((0x1UL << (10U)))) == ((0x1UL << (10U)))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->CIER) & ((0x1UL << (9U)))) == ((0x1UL << (9U)))) ? 1UL : 0UL);
}



 




 
ErrorStatus LL_RCC_DeInit(void);


 



 
void        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
uint32_t    LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);

uint32_t    LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);

uint32_t    LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
uint32_t    LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
uint32_t    LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
uint32_t    LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
uint32_t    LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);

uint32_t    LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);

uint32_t    LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
uint32_t    LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
uint32_t    LL_RCC_GetADCClockFreq(uint32_t ADCxSource);

uint32_t    LL_RCC_GetQUADSPIClockFreq(uint32_t QUADSPIxSource);



 




 



 



 







#line 37 "../Core/Inc/main.h"
#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h"
































 

 







 
#line 45 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h"



 





 

 
 

 

 

 
 


 



 
#line 81 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h"


 



 
#line 114 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h"


 



 
#line 128 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h"


 



 
#line 166 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h"


 




 
#line 180 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h"


 



 
#line 206 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h"


 



 

 
 


 



 



















 
static __inline void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
{
  volatile uint32_t tmpreg;
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->AHB1ENR) |= (Periphs));
   
  tmpreg = ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->AHB1ENR) & (Periphs));
  (void)tmpreg;
}



















 
static __inline uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->AHB1ENR) & (Periphs)) == Periphs) ? 1UL : 0UL);
}



















 
static __inline void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->AHB1ENR) &= ~(Periphs));
}




















 
static __inline void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->AHB1RSTR) |= (Periphs));
}




















 
static __inline void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->AHB1RSTR) &= ~(Periphs));
}





















 
static __inline void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
{
  volatile uint32_t tmpreg;
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->AHB1SMENR) |= (Periphs));
   
  tmpreg = ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->AHB1SMENR) & (Periphs));
  (void)tmpreg;
}





















 
static __inline void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->AHB1SMENR) &= ~(Periphs));
}



 



 





































 
static __inline void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
{
  volatile uint32_t tmpreg;
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->AHB2ENR) |= (Periphs));
   
  tmpreg = ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->AHB2ENR) & (Periphs));
  (void)tmpreg;
}





































 
static __inline uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->AHB2ENR) & (Periphs)) == Periphs) ? 1UL : 0UL);
}





































 
static __inline void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->AHB2ENR) &= ~(Periphs));
}





































 
static __inline void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->AHB2RSTR) |= (Periphs));
}





































 
static __inline void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->AHB2RSTR) &= ~(Periphs));
}









































 
static __inline void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
{
  volatile uint32_t tmpreg;
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->AHB2SMENR) |= (Periphs));
   
  tmpreg = ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->AHB2SMENR) & (Periphs));
  (void)tmpreg;
}









































 
static __inline void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->AHB2SMENR) &= ~(Periphs));
}



 



 











 
static __inline void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
{
  volatile uint32_t tmpreg;
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->AHB3ENR) |= (Periphs));
   
  tmpreg = ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->AHB3ENR) & (Periphs));
  (void)tmpreg;
}











 
static __inline uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->AHB3ENR) & (Periphs)) == Periphs) ? 1UL : 0UL);
}











 
static __inline void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->AHB3ENR) &= ~(Periphs));
}












 
static __inline void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->AHB3RSTR) |= (Periphs));
}












 
static __inline void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->AHB3RSTR) &= ~(Periphs));
}











 
static __inline void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs)
{
  volatile uint32_t tmpreg;
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->AHB3SMENR) |= (Periphs));
   
  tmpreg = ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->AHB3SMENR) & (Periphs));
  (void)tmpreg;
}











 
static __inline void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->AHB3SMENR) &= ~(Periphs));
}



 



 



















































 
static __inline void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
{
  volatile uint32_t tmpreg;
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->APB1ENR1) |= (Periphs));
   
  tmpreg = ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->APB1ENR1) & (Periphs));
  (void)tmpreg;
}













 
static __inline void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
{
  volatile uint32_t tmpreg;
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->APB1ENR2) |= (Periphs));
   
  tmpreg = ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->APB1ENR2) & (Periphs));
  (void)tmpreg;
}



















































 
static __inline uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->APB1ENR1) & (Periphs)) == Periphs) ? 1UL : 0UL);
}













 
static __inline uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->APB1ENR2) & (Periphs)) == Periphs) ? 1UL : 0UL);
}



















































 
static __inline void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->APB1ENR1) &= ~(Periphs));
}













 
static __inline void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->APB1ENR2) &= ~(Periphs));
}















































 
static __inline void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->APB1RSTR1) |= (Periphs));
}













 
static __inline void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->APB1RSTR2) |= (Periphs));
}















































 
static __inline void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->APB1RSTR1) &= ~(Periphs));
}













 
static __inline void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->APB1RSTR2) &= ~(Periphs));
}



















































 
static __inline void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
{
  volatile uint32_t tmpreg;
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->APB1SMENR1) |= (Periphs));
   
  tmpreg = ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->APB1SMENR1) & (Periphs));
  (void)tmpreg;
}













 
static __inline void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)
{
  volatile uint32_t tmpreg;
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->APB1SMENR2) |= (Periphs));
   
  tmpreg = ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->APB1SMENR2) & (Periphs));
  (void)tmpreg;
}



















































 
static __inline void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->APB1SMENR1) &= ~(Periphs));
}













 
static __inline void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->APB1SMENR2) &= ~(Periphs));
}



 



 































 
static __inline void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
{
  volatile uint32_t tmpreg;
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->APB2ENR) |= (Periphs));
   
  tmpreg = ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->APB2ENR) & (Periphs));
  (void)tmpreg;
}































 
static __inline uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
{
  return ((((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->APB2ENR) & (Periphs)) == Periphs) ? 1UL : 0UL);
}































 
static __inline void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->APB2ENR) &= ~(Periphs));
}































 
static __inline void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->APB2RSTR) |= (Periphs));
}































 
static __inline void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->APB2RSTR) &= ~(Periphs));
}































 
static __inline void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
{
  volatile uint32_t tmpreg;
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->APB2SMENR) |= (Periphs));
   
  tmpreg = ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->APB2SMENR) & (Periphs));
  (void)tmpreg;
}































 
static __inline void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
{
  ((((RCC_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x1000UL))->APB2SMENR) &= ~(Periphs));
}



 




 



 





 







#line 38 "../Core/Inc/main.h"
#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_crs.h"
















 

 







 
#line 29 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_crs.h"



 





 

 
 
 
 

 
 


 




 
#line 62 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_crs.h"


 




 






 



 
#line 89 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_crs.h"


 



 





 



 




 



 




 



 




 




 







 



 


 

 


 



 







 







 



 



 











 




 



 

 


 



 






 
static __inline void LL_CRS_EnableFreqErrorCounter(void)
{
  ((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CR) |= ((0x1UL << (5U))));
}





 
static __inline void LL_CRS_DisableFreqErrorCounter(void)
{
  ((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CR) &= ~((0x1UL << (5U))));
}





 
static __inline uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
{
  return ((((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CR) & ((0x1UL << (5U)))) == ((0x1UL << (5U)))) ? 1UL : 0UL);
}





 
static __inline void LL_CRS_EnableAutoTrimming(void)
{
  ((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CR) |= ((0x1UL << (6U))));
}





 
static __inline void LL_CRS_DisableAutoTrimming(void)
{
  ((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CR) &= ~((0x1UL << (6U))));
}





 
static __inline uint32_t LL_CRS_IsEnabledAutoTrimming(void)
{
  return ((((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CR) & ((0x1UL << (6U)))) == ((0x1UL << (6U)))) ? 1UL : 0UL);
}








 
static __inline void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
{
  (((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CR)) = ((((((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CR))) & (~((0x7FUL << (8U))))) | (Value << (8U)))));
}





 
static __inline uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
{
  return (uint32_t)(((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CR) & ((0x7FUL << (8U)))) >> (8U));
}








 
static __inline void LL_CRS_SetReloadCounter(uint32_t Value)
{
  (((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CFGR)) = ((((((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CFGR))) & (~((0xFFFFUL << (0U))))) | (Value))));
}





 
static __inline uint32_t LL_CRS_GetReloadCounter(void)
{
  return (uint32_t)(((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CFGR) & ((0xFFFFUL << (0U)))));
}







 
static __inline void LL_CRS_SetFreqErrorLimit(uint32_t Value)
{
  (((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CFGR)) = ((((((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CFGR))) & (~((0xFFUL << (16U))))) | (Value << (16U)))));
}





 
static __inline uint32_t LL_CRS_GetFreqErrorLimit(void)
{
  return (uint32_t)(((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CFGR) & ((0xFFUL << (16U)))) >> (16U));
}














 
static __inline void LL_CRS_SetSyncDivider(uint32_t Divider)
{
  (((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CFGR)) = ((((((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CFGR))) & (~((0x7UL << (24U))))) | (Divider))));
}













 
static __inline uint32_t LL_CRS_GetSyncDivider(void)
{
  return (uint32_t)(((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CFGR) & ((0x7UL << (24U)))));
}









 
static __inline void LL_CRS_SetSyncSignalSource(uint32_t Source)
{
  (((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CFGR)) = ((((((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CFGR))) & (~((0x3UL << (28U))))) | (Source))));
}








 
static __inline uint32_t LL_CRS_GetSyncSignalSource(void)
{
  return (uint32_t)(((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CFGR) & ((0x3UL << (28U)))));
}








 
static __inline void LL_CRS_SetSyncPolarity(uint32_t Polarity)
{
  (((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CFGR)) = ((((((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CFGR))) & (~((0x1UL << (31U))))) | (Polarity))));
}







 
static __inline uint32_t LL_CRS_GetSyncPolarity(void)
{
  return (uint32_t)(((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CFGR) & ((0x1UL << (31U)))));
}


















 
static __inline void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue,
                                                  uint32_t ReloadValue, uint32_t Settings)
{
  (((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CR)) = ((((((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CR))) & (~((0x7FUL << (8U))))) | (HSI48CalibrationValue))));
  (((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CFGR)) = ((((((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CFGR))) & (~((0xFFFFUL << (0U)) | (0xFFUL << (16U)) | (0x7UL << (24U)) | (0x3UL << (28U)) | (0x1UL << (31U))))) | (ReloadValue | (ErrorLimitValue << (16U)) | Settings))));


}



 



 





 
static __inline void LL_CRS_GenerateEvent_SWSYNC(void)
{
  ((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CR) |= ((0x1UL << (7U))));
}








 
static __inline uint32_t LL_CRS_GetFreqErrorDirection(void)
{
  return (uint32_t)(((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->ISR) & ((0x1UL << (15U)))));
}





 
static __inline uint32_t LL_CRS_GetFreqErrorCapture(void)
{
  return (uint32_t)(((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->ISR) & ((0xFFFFUL << (16U)))) >> (16U));
}



 



 





 
static __inline uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
{
  return ((((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->ISR) & ((0x1UL << (0U)))) == ((0x1UL << (0U)))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
{
  return ((((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->ISR) & ((0x1UL << (1U)))) == ((0x1UL << (1U)))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_CRS_IsActiveFlag_ERR(void)
{
  return ((((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->ISR) & ((0x1UL << (2U)))) == ((0x1UL << (2U)))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
{
  return ((((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->ISR) & ((0x1UL << (3U)))) == ((0x1UL << (3U)))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
{
  return ((((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->ISR) & ((0x1UL << (8U)))) == ((0x1UL << (8U)))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
{
  return ((((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->ISR) & ((0x1UL << (9U)))) == ((0x1UL << (9U)))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
{
  return ((((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->ISR) & ((0x1UL << (10U)))) == ((0x1UL << (10U)))) ? 1UL : 0UL);
}





 
static __inline void LL_CRS_ClearFlag_SYNCOK(void)
{
  ((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->ICR) = ((0x1UL << (0U))));
}





 
static __inline void LL_CRS_ClearFlag_SYNCWARN(void)
{
  ((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->ICR) = ((0x1UL << (1U))));
}






 
static __inline void LL_CRS_ClearFlag_ERR(void)
{
  ((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->ICR) = ((0x1UL << (2U))));
}





 
static __inline void LL_CRS_ClearFlag_ESYNC(void)
{
  ((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->ICR) = ((0x1UL << (3U))));
}



 



 





 
static __inline void LL_CRS_EnableIT_SYNCOK(void)
{
  ((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CR) |= ((0x1UL << (0U))));
}





 
static __inline void LL_CRS_DisableIT_SYNCOK(void)
{
  ((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CR) &= ~((0x1UL << (0U))));
}





 
static __inline uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
{
  return ((((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CR) & ((0x1UL << (0U)))) == ((0x1UL << (0U)))) ? 1UL : 0UL);
}





 
static __inline void LL_CRS_EnableIT_SYNCWARN(void)
{
  ((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CR) |= ((0x1UL << (1U))));
}





 
static __inline void LL_CRS_DisableIT_SYNCWARN(void)
{
  ((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CR) &= ~((0x1UL << (1U))));
}





 
static __inline uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
{
  return ((((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CR) & ((0x1UL << (1U)))) == ((0x1UL << (1U)))) ? 1UL : 0UL);
}





 
static __inline void LL_CRS_EnableIT_ERR(void)
{
  ((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CR) |= ((0x1UL << (2U))));
}





 
static __inline void LL_CRS_DisableIT_ERR(void)
{
  ((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CR) &= ~((0x1UL << (2U))));
}





 
static __inline uint32_t LL_CRS_IsEnabledIT_ERR(void)
{
  return ((((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CR) & ((0x1UL << (2U)))) == ((0x1UL << (2U)))) ? 1UL : 0UL);
}





 
static __inline void LL_CRS_EnableIT_ESYNC(void)
{
  ((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CR) |= ((0x1UL << (3U))));
}





 
static __inline void LL_CRS_DisableIT_ESYNC(void)
{
  ((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CR) &= ~((0x1UL << (3U))));
}





 
static __inline uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
{
  return ((((((CRS_TypeDef *) ((0x40000000UL) + 0x2000UL))->CR) & ((0x1UL << (3U)))) == ((0x1UL << (3U)))) ? 1UL : 0UL);
}



 




 

ErrorStatus LL_CRS_DeInit(void);



 




 



 





 







#line 39 "../Core/Inc/main.h"
#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h"






























 

 







 
#line 43 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h"



 





 

 
 

 


 

 




 






 

 

 
 


 



 
#line 94 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h"


 




 






 




 
#line 130 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h"


 



 
#line 144 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h"


 



 
#line 167 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h"


 



 
#line 183 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h"


 



 
#line 224 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h"


 



 







 



 
#line 266 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h"


 



 





 



 
#line 298 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h"


 




 





 




 
#line 335 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h"


 



 

 

 


 



 













 
static __inline void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
{
  (((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->MEMRMP)) = ((((((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->MEMRMP))) & (~((0x7UL << (0U))))) | (Memory))));
}












 
static __inline uint32_t LL_SYSCFG_GetRemapMemory(void)
{
  return (uint32_t)(((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->MEMRMP) & ((0x7UL << (0U)))));
}









 
static __inline void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
{
  (((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->MEMRMP)) = ((((((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->MEMRMP))) & (~((0x1UL << (8U))))) | (Bank))));
}







 
static __inline uint32_t LL_SYSCFG_GetFlashBankMode(void)
{
  return (uint32_t)(((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->MEMRMP) & ((0x1UL << (8U)))));
}















 
static __inline void LL_SYSCFG_EnableAnalogBooster(void)
{
  ((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->CFGR1) |= ((0x1UL << (8U))));
}














 
static __inline void LL_SYSCFG_DisableAnalogBooster(void)
{
  ((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->CFGR1) &= ~((0x1UL << (8U))));
}

















 
static __inline void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
{
  ((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->CFGR1) |= (ConfigFastModePlus));
}

















 
static __inline void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
{
  ((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->CFGR1) &= ~(ConfigFastModePlus));
}





 
static __inline void LL_SYSCFG_EnableIT_FPU_IOC(void)
{
  ((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->CFGR1) |= ((0x04000000U)));
}





 
static __inline void LL_SYSCFG_EnableIT_FPU_DZC(void)
{
  ((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->CFGR1) |= ((0x08000000U)));
}





 
static __inline void LL_SYSCFG_EnableIT_FPU_UFC(void)
{
  ((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->CFGR1) |= ((0x10000000U)));
}





 
static __inline void LL_SYSCFG_EnableIT_FPU_OFC(void)
{
  ((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->CFGR1) |= ((0x20000000U)));
}





 
static __inline void LL_SYSCFG_EnableIT_FPU_IDC(void)
{
  ((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->CFGR1) |= ((0x40000000U)));
}





 
static __inline void LL_SYSCFG_EnableIT_FPU_IXC(void)
{
  ((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->CFGR1) |= ((0x80000000U)));
}





 
static __inline void LL_SYSCFG_DisableIT_FPU_IOC(void)
{
  ((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->CFGR1) &= ~((0x04000000U)));
}





 
static __inline void LL_SYSCFG_DisableIT_FPU_DZC(void)
{
  ((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->CFGR1) &= ~((0x08000000U)));
}





 
static __inline void LL_SYSCFG_DisableIT_FPU_UFC(void)
{
  ((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->CFGR1) &= ~((0x10000000U)));
}





 
static __inline void LL_SYSCFG_DisableIT_FPU_OFC(void)
{
  ((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->CFGR1) &= ~((0x20000000U)));
}





 
static __inline void LL_SYSCFG_DisableIT_FPU_IDC(void)
{
  ((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->CFGR1) &= ~((0x40000000U)));
}





 
static __inline void LL_SYSCFG_DisableIT_FPU_IXC(void)
{
  ((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->CFGR1) &= ~((0x80000000U)));
}





 
static __inline uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
{
  return ((((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->CFGR1) & ((0x04000000U))) == ((0x04000000U))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
{
  return ((((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->CFGR1) & ((0x08000000U))) == ((0x08000000U))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
{
  return ((((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->CFGR1) & ((0x10000000U))) == ((0x10000000U))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
{
  return ((((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->CFGR1) & ((0x20000000U))) == ((0x20000000U))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
{
  return ((((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->CFGR1) & ((0x40000000U))) == ((0x40000000U))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
{
  return ((((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->CFGR1) & ((0x80000000U))) == ((0x80000000U))) ? 1UL : 0UL);
}



































 
static __inline void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
{
  (((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->EXTICR[Line & 0x3U])) = ((((((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->EXTICR[Line & 0x3U]))) & (~((Line >> 16U)))) | (Port << ((__clz(__rbit((Line >> 16U)))) & 0x1FU)))));
}


































 
static __inline uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
{
  return (uint32_t)(((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->EXTICR[Line & 0x3U]) & ((Line >> 16U))) >> ((__clz(__rbit(Line >> 16U))) & 0x1FU));
}









 
static __inline void LL_SYSCFG_EnableCCMSRAMErase(void)
{
   
  ((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->SCSR) |= ((0x1UL << (0U))));
}





 
static __inline uint32_t LL_SYSCFG_IsCCMSRAMEraseOngoing(void)
{
  return ((((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->SCSR) & ((0x1UL << (1U)))) == ((0x1UL << (1U)))) ? 1UL : 0UL);
}













 
static __inline void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
{
  (((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->CFGR2)) = ((((((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->CFGR2))) & (~((0x1UL << (0U)) | (0x1UL << (1U)) | (0x1UL << (2U)) | (0x1UL << (3U))))) | (Break))));
}












 
static __inline uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
{
  return (uint32_t)(((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->CFGR2) & ((0x1UL << (0U)) | (0x1UL << (1U)) | (0x1UL << (2U)) | (0x1UL << (3U)))));
}





 
static __inline uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
{
  return ((((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->CFGR2) & ((0x1UL << (8U)))) == ((0x1UL << (8U)))) ? 1UL : 0UL);
}





 
static __inline void LL_SYSCFG_ClearFlag_SP(void)
{
  ((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->CFGR2) |= ((0x1UL << (8U))));
}









































 
static __inline void LL_SYSCFG_EnableCCMSRAMPageWRP(uint32_t CCMSRAMWRP)
{
  ((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->SWPR) |= (CCMSRAMWRP));
}





 
static __inline void LL_SYSCFG_LockCCMSRAMWRP(void)
{
   
  ((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->SKR) = (0x00));
}





 
static __inline void LL_SYSCFG_UnlockCCMSRAMWRP(void)
{
   
  ((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->SKR) = (0xCA));
  ((((SYSCFG_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0000UL))->SKR) = (0x53));
}



 




 





 
static __inline uint32_t LL_DBGMCU_GetDeviceID(void)
{
  return (uint32_t)(((((DBGMCU_TypeDef *) (0xE0042000UL))->IDCODE) & ((0xFFFUL << (0U)))));
}






 
static __inline uint32_t LL_DBGMCU_GetRevisionID(void)
{
  return (uint32_t)(((((DBGMCU_TypeDef *) (0xE0042000UL))->IDCODE) & ((0xFFFFUL << (16U)))) >> ((uint32_t)(__clz(__rbit((0xFFFFUL << (16U))))) & 0x1FU));
}





 
static __inline void LL_DBGMCU_EnableDBGSleepMode(void)
{
  ((((DBGMCU_TypeDef *) (0xE0042000UL))->CR) |= ((0x1UL << (0U))));
}





 
static __inline void LL_DBGMCU_DisableDBGSleepMode(void)
{
  ((((DBGMCU_TypeDef *) (0xE0042000UL))->CR) &= ~((0x1UL << (0U))));
}





 
static __inline void LL_DBGMCU_EnableDBGStopMode(void)
{
  ((((DBGMCU_TypeDef *) (0xE0042000UL))->CR) |= ((0x1UL << (1U))));
}





 
static __inline void LL_DBGMCU_DisableDBGStopMode(void)
{
  ((((DBGMCU_TypeDef *) (0xE0042000UL))->CR) &= ~((0x1UL << (1U))));
}





 
static __inline void LL_DBGMCU_EnableDBGStandbyMode(void)
{
  ((((DBGMCU_TypeDef *) (0xE0042000UL))->CR) |= ((0x1UL << (2U))));
}





 
static __inline void LL_DBGMCU_DisableDBGStandbyMode(void)
{
  ((((DBGMCU_TypeDef *) (0xE0042000UL))->CR) &= ~((0x1UL << (2U))));
}












 
static __inline void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
{
  (((((DBGMCU_TypeDef *) (0xE0042000UL))->CR)) = ((((((((DBGMCU_TypeDef *) (0xE0042000UL))->CR))) & (~((0x1UL << (5U)) | (0x3UL << (6U))))) | (PinAssignment))));
}











 
static __inline uint32_t LL_DBGMCU_GetTracePinAssignment(void)
{
  return (uint32_t)(((((DBGMCU_TypeDef *) (0xE0042000UL))->CR) & ((0x1UL << (5U)) | (0x3UL << (6U)))));
}





















 
static __inline void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
{
  ((((DBGMCU_TypeDef *) (0xE0042000UL))->APB1FZR1) |= (Periphs));
}









 
static __inline void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
{
  ((((DBGMCU_TypeDef *) (0xE0042000UL))->APB1FZR2) |= (Periphs));
}





















 
static __inline void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
{
  ((((DBGMCU_TypeDef *) (0xE0042000UL))->APB1FZR1) &= ~(Periphs));
}









 
static __inline void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
{
  ((((DBGMCU_TypeDef *) (0xE0042000UL))->APB1FZR2) &= ~(Periphs));
}















 
static __inline void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
{
  ((((DBGMCU_TypeDef *) (0xE0042000UL))->APB2FZ) |= (Periphs));
}















 
static __inline void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
{
  ((((DBGMCU_TypeDef *) (0xE0042000UL))->APB2FZ) &= ~(Periphs));
}



 




 





 
static __inline void LL_VREFBUF_Enable(void)
{
  ((((VREFBUF_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0030UL))->CSR) |= ((0x1UL << (0U))));
}





 
static __inline void LL_VREFBUF_Disable(void)
{
  ((((VREFBUF_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0030UL))->CSR) &= ~((0x1UL << (0U))));
}





 
static __inline void LL_VREFBUF_EnableHIZ(void)
{
  ((((VREFBUF_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0030UL))->CSR) |= ((0x1UL << (1U))));
}





 
static __inline void LL_VREFBUF_DisableHIZ(void)
{
  ((((VREFBUF_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0030UL))->CSR) &= ~((0x1UL << (1U))));
}









 
static __inline void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
{
  (((((VREFBUF_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0030UL))->CSR)) = ((((((((VREFBUF_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0030UL))->CSR))) & (~((0x3UL << (4U))))) | (Scale))));
}








 
static __inline uint32_t LL_VREFBUF_GetVoltageScaling(void)
{
  return (uint32_t)(((((VREFBUF_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0030UL))->CSR) & ((0x3UL << (4U)))));
}





 
static __inline uint32_t LL_VREFBUF_IsVREFReady(void)
{
  return ((((((VREFBUF_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0030UL))->CSR) & ((0x1UL << (3U)))) == ((0x1UL << (3U)))) ? 1UL : 0UL);
}





 
static __inline uint32_t LL_VREFBUF_GetTrimming(void)
{
  return (uint32_t)(((((VREFBUF_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0030UL))->CCR) & ((0x3FUL << (0U)))));
}






 
static __inline void LL_VREFBUF_SetTrimming(uint32_t Value)
{
  ((((VREFBUF_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0030UL))->CCR) = (Value));
}



 




 
























 
static __inline void LL_FLASH_SetLatency(uint32_t Latency)
{
  (((((FLASH_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x2000UL))->ACR)) = ((((((((FLASH_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x2000UL))->ACR))) & (~((0xFUL << (0U))))) | (Latency))));
}























 
static __inline uint32_t LL_FLASH_GetLatency(void)
{
  return (uint32_t)(((((FLASH_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x2000UL))->ACR) & ((0xFUL << (0U)))));
}





 
static __inline void LL_FLASH_EnablePrefetch(void)
{
  ((((FLASH_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x2000UL))->ACR) |= ((0x1UL << (8U))));
}





 
static __inline void LL_FLASH_DisablePrefetch(void)
{
  ((((FLASH_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x2000UL))->ACR) &= ~((0x1UL << (8U))));
}





 
static __inline uint32_t LL_FLASH_IsPrefetchEnabled(void)
{
  return ((((((FLASH_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x2000UL))->ACR) & ((0x1UL << (8U)))) == ((0x1UL << (8U)))) ? 1UL : 0UL);
}





 
static __inline void LL_FLASH_EnableInstCache(void)
{
  ((((FLASH_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x2000UL))->ACR) |= ((0x1UL << (9U))));
}





 
static __inline void LL_FLASH_DisableInstCache(void)
{
  ((((FLASH_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x2000UL))->ACR) &= ~((0x1UL << (9U))));
}





 
static __inline void LL_FLASH_EnableDataCache(void)
{
  ((((FLASH_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x2000UL))->ACR) |= ((0x1UL << (10U))));
}





 
static __inline void LL_FLASH_DisableDataCache(void)
{
  ((((FLASH_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x2000UL))->ACR) &= ~((0x1UL << (10U))));
}






 
static __inline void LL_FLASH_EnableInstCacheReset(void)
{
  ((((FLASH_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x2000UL))->ACR) |= ((0x1UL << (11U))));
}





 
static __inline void LL_FLASH_DisableInstCacheReset(void)
{
  ((((FLASH_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x2000UL))->ACR) &= ~((0x1UL << (11U))));
}






 
static __inline void LL_FLASH_EnableDataCacheReset(void)
{
  ((((FLASH_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x2000UL))->ACR) |= ((0x1UL << (12U))));
}





 
static __inline void LL_FLASH_DisableDataCacheReset(void)
{
  ((((FLASH_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x2000UL))->ACR) &= ~((0x1UL << (12U))));
}












 
static __inline void LL_FLASH_EnableRunPowerDown(void)
{
  
 
  ((((FLASH_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x2000UL))->PDKEYR) = (0x04152637U));
  ((((FLASH_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x2000UL))->PDKEYR) = (0xFAFBFCFDU));
  ((((FLASH_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x2000UL))->ACR) |= ((0x1UL << (13U))));
}







 
static __inline void LL_FLASH_DisableRunPowerDown(void)
{
  
 
  ((((FLASH_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x2000UL))->PDKEYR) = (0x04152637U));
  ((((FLASH_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x2000UL))->PDKEYR) = (0xFAFBFCFDU));
  ((((FLASH_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x2000UL))->ACR) &= ~((0x1UL << (13U))));
}







 
static __inline void LL_FLASH_EnableSleepPowerDown(void)
{
  ((((FLASH_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x2000UL))->ACR) |= ((0x1UL << (14U))));
}





 
static __inline void LL_FLASH_DisableSleepPowerDown(void)
{
  ((((FLASH_TypeDef *) (((0x40000000UL) + 0x00020000UL) + 0x2000UL))->ACR) &= ~((0x1UL << (14U))));
}



 



 



 





 







#line 40 "../Core/Inc/main.h"
#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_exti.h"
















 

 







 
#line 29 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_exti.h"



 





 

 
 
 
 



 


 

 



 
typedef struct
{

  uint32_t Line_0_31;           
 

  uint32_t Line_32_63;          
 

  FunctionalState LineCommand;  
 

  uint8_t Mode;                 
 

  uint8_t Trigger;              
 
} LL_EXTI_InitTypeDef;



 


 


 



 
#line 148 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_exti.h"

#line 183 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_exti.h"










 




 





 



 







 







 

 


 



 






 






 



 




 



 


 


 












































 
static __inline void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
{
  ((((EXTI_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0400UL))->IMR1) |= (ExtiLine));
}





















 
static __inline void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine)
{
  ((((EXTI_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0400UL))->IMR2) |= (ExtiLine));
}












































 
static __inline void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
{
  ((((EXTI_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0400UL))->IMR1) &= ~(ExtiLine));
}






















 
static __inline void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine)
{
  ((((EXTI_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0400UL))->IMR2) &= ~(ExtiLine));
}












































 
static __inline uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
{
  return ((((((EXTI_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0400UL))->IMR1) & (ExtiLine)) == (ExtiLine)) ? 1UL : 0UL);
}






















 
static __inline uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)
{
  return ((((((EXTI_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0400UL))->IMR2) & (ExtiLine)) == (ExtiLine)) ? 1UL : 0UL);
}



 



 









































 
static __inline void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
{
  ((((EXTI_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0400UL))->EMR1) |= (ExtiLine));

}



















 
static __inline void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
{
  ((((EXTI_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0400UL))->EMR2) |= (ExtiLine));
}









































 
static __inline void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
{
  ((((EXTI_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0400UL))->EMR1) &= ~(ExtiLine));
}



















 
static __inline void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
{
  ((((EXTI_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0400UL))->EMR2) &= ~(ExtiLine));
}









































 
static __inline uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
{
  return ((((((EXTI_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0400UL))->EMR1) & (ExtiLine)) == (ExtiLine)) ? 1UL : 0UL);

}



















 
static __inline uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)
{
  return ((((((EXTI_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0400UL))->EMR2) & (ExtiLine)) == (ExtiLine)) ? 1UL : 0UL);
}



 



 








































 
static __inline void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
{
  ((((EXTI_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0400UL))->RTSR1) |= (ExtiLine));

}



















 
static __inline void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine)
{
  ((((EXTI_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0400UL))->RTSR2) |= (ExtiLine));
}








































 
static __inline void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
{
  ((((EXTI_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0400UL))->RTSR1) &= ~(ExtiLine));

}




















 
static __inline void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine)
{
  ((((EXTI_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0400UL))->RTSR2) &= ~(ExtiLine));
}

































 
static __inline uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
{
  return ((((((EXTI_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0400UL))->RTSR1) & (ExtiLine)) == (ExtiLine)) ? 1UL : 0UL);
}













 
static __inline uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine)
{
  return ((((((EXTI_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0400UL))->RTSR2) & (ExtiLine)) == (ExtiLine)) ? 1UL : 0UL);
}



 



 








































 
static __inline void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
{
  ((((EXTI_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0400UL))->FTSR1) |= (ExtiLine));
}




















 
static __inline void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine)
{
  ((((EXTI_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0400UL))->FTSR2) |= (ExtiLine));
}







































 
static __inline void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
{
  ((((EXTI_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0400UL))->FTSR1) &= ~(ExtiLine));
}



















 
static __inline void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine)
{
  ((((EXTI_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0400UL))->FTSR2) &= ~(ExtiLine));
}

































 
static __inline uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
{
  return ((((((EXTI_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0400UL))->FTSR1) & (ExtiLine)) == (ExtiLine)) ? 1UL : 0UL);
}













 
static __inline uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine)
{
  return ((((((EXTI_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0400UL))->FTSR2) & (ExtiLine)) == (ExtiLine)) ? 1UL : 0UL);
}



 



 






































 
static __inline void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
{
  ((((EXTI_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0400UL))->SWIER1) |= (ExtiLine));
}


















 
static __inline void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine)
{
  ((((EXTI_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0400UL))->SWIER2) |= (ExtiLine));
}



 



 



































 
static __inline uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
{
  return ((((((EXTI_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0400UL))->PR1) & (ExtiLine)) == (ExtiLine)) ? 1UL : 0UL);
}















 
static __inline uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine)
{
  return ((((((EXTI_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0400UL))->PR2) & (ExtiLine)) == (ExtiLine)) ? 1UL : 0UL);
}



































 
static __inline uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
{
  return (uint32_t)(((((EXTI_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0400UL))->PR1) & (ExtiLine)));
}















 
static __inline uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine)
{
  return (uint32_t)(((((EXTI_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0400UL))->PR2) & (ExtiLine)));
}



































 
static __inline void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
{
  ((((EXTI_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0400UL))->PR1) = (ExtiLine));
}















 
static __inline void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine)
{
  ((((EXTI_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x0400UL))->PR2) = (ExtiLine));
}



 




 

uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
uint32_t LL_EXTI_DeInit(void);
void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);




 




 



 





 







#line 41 "../Core/Inc/main.h"
#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cortex.h"































 

 







 
#line 44 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cortex.h"



 



 

 
 

 

 

 
 


 



 




 



 





 





 






 



 
#line 109 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cortex.h"


 



 
#line 144 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cortex.h"


 



 
#line 157 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cortex.h"


 



 






 



 




 



 




 



 




 



 




 



 

 

 


 



 






 
static __inline uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
{
  return (((((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->CTRL & (1UL << 16U)) == ((1UL << 16U))) ? 1UL : 0UL);
}








 
static __inline void LL_SYSTICK_SetClkSource(uint32_t Source)
{
  if (Source == (1UL << 2U))
  {
    ((((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->CTRL) |= ((1UL << 2U)));
  }
  else
  {
    ((((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->CTRL) &= ~((1UL << 2U)));
  }
}







 
static __inline uint32_t LL_SYSTICK_GetClkSource(void)
{
  return ((((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->CTRL) & ((1UL << 2U)));
}





 
static __inline void LL_SYSTICK_EnableIT(void)
{
  ((((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->CTRL) |= ((1UL << 1U)));
}





 
static __inline void LL_SYSTICK_DisableIT(void)
{
  ((((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->CTRL) &= ~((1UL << 1U)));
}





 
static __inline uint32_t LL_SYSTICK_IsEnabledIT(void)
{
  return ((((((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->CTRL) & ((1UL << 1U))) == ((1UL << 1U))) ? 1UL : 0UL);
}



 



 





 
static __inline void LL_LPM_EnableSleep(void)
{
   
  ((((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SCR) &= ~(((uint32_t)(1UL << 2U))));
}





 
static __inline void LL_LPM_EnableDeepSleep(void)
{
   
  ((((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SCR) |= (((uint32_t)(1UL << 2U))));
}







 
static __inline void LL_LPM_EnableSleepOnExit(void)
{
   
  ((((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SCR) |= (((uint32_t)(1UL << 1U))));
}





 
static __inline void LL_LPM_DisableSleepOnExit(void)
{
   
  ((((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SCR) &= ~(((uint32_t)(1UL << 1U))));
}






 
static __inline void LL_LPM_EnableEventOnPend(void)
{
   
  ((((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SCR) |= (((uint32_t)(1UL << 4U))));
}






 
static __inline void LL_LPM_DisableEventOnPend(void)
{
   
  ((((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SCR) &= ~(((uint32_t)(1UL << 4U))));
}



 



 









 
static __inline void LL_HANDLER_EnableFault(uint32_t Fault)
{
   
  ((((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHCSR) |= (Fault));
}









 
static __inline void LL_HANDLER_DisableFault(uint32_t Fault)
{
   
  ((((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHCSR) &= ~(Fault));
}



 



 





 
static __inline uint32_t LL_CPUID_GetImplementer(void)
{
  return (uint32_t)(((((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->CPUID) & ((0xFFUL << 24U))) >> 24U);
}





 
static __inline uint32_t LL_CPUID_GetVariant(void)
{
  return (uint32_t)(((((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->CPUID) & ((0xFUL << 20U))) >> 20U);
}





 
static __inline uint32_t LL_CPUID_GetArchitecture(void)
{
  return (uint32_t)(((((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->CPUID) & ((0xFUL << 16U))) >> 16U);
}





 
static __inline uint32_t LL_CPUID_GetParNo(void)
{
  return (uint32_t)(((((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->CPUID) & ((0xFFFUL << 4U))) >> 4U);
}





 
static __inline uint32_t LL_CPUID_GetRevision(void)
{
  return (uint32_t)(((((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->CPUID) & ((0xFUL ))) >> 0U);
}



 




 










 
static __inline void LL_MPU_Enable(uint32_t Options)
{
   
  ((((MPU_Type *) ((0xE000E000UL) + 0x0D90UL) )->CTRL) = (((1UL ) | Options)));
   
  do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U);
   
  do { __schedule_barrier(); __isb(0xF); __schedule_barrier(); } while (0U);
}





 
static __inline void LL_MPU_Disable(void)
{
   
  do { __schedule_barrier(); __dmb(0xF); __schedule_barrier(); } while (0U);
   
  ((((MPU_Type *) ((0xE000E000UL) + 0x0D90UL) )->CTRL) = (0U));
}





 
static __inline uint32_t LL_MPU_IsEnabled(void)
{
  return ((((((MPU_Type *) ((0xE000E000UL) + 0x0D90UL) )->CTRL) & ((1UL ))) == ((1UL ))) ? 1UL : 0UL);
}














 
static __inline void LL_MPU_EnableRegion(uint32_t Region)
{
   
  ((((MPU_Type *) ((0xE000E000UL) + 0x0D90UL) )->RNR) = (Region));
   
  ((((MPU_Type *) ((0xE000E000UL) + 0x0D90UL) )->RASR) |= ((1UL )));
}






































 
static __inline void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
{
   
  ((((MPU_Type *) ((0xE000E000UL) + 0x0D90UL) )->RNR) = (Region));
   
  ((((MPU_Type *) ((0xE000E000UL) + 0x0D90UL) )->RBAR) = ((Address & 0xFFFFFFE0U)));
   
  ((((MPU_Type *) ((0xE000E000UL) + 0x0D90UL) )->RASR) = (((1UL ) | Attributes | (SubRegionDisable << 8U))));
}















 
static __inline void LL_MPU_DisableRegion(uint32_t Region)
{
   
  ((((MPU_Type *) ((0xE000E000UL) + 0x0D90UL) )->RNR) = (Region));
   
  ((((MPU_Type *) ((0xE000E000UL) + 0x0D90UL) )->RASR) &= ~((1UL )));
}



 




 



 



 







#line 42 "../Core/Inc/main.h"
#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_utils.h"




























 

 







 
#line 41 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_utils.h"



 



 

 
 

 


 

 




 




 




 




 

 


 


 
 


 


 
typedef struct
{
  uint32_t PLLM;   



 

  uint32_t PLLN;   



 

  uint32_t PLLR;   



 
} LL_UTILS_PLLInitTypeDef;



 
typedef struct
{
  uint32_t AHBCLKDivider;         



 

  uint32_t APB1CLKDivider;        



 

  uint32_t APB2CLKDivider;        



 

} LL_UTILS_ClkInitTypeDef;



 

 


 



 




 



 
#line 173 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_utils.h"



 



 

 

 


 



 




 
static __inline uint32_t LL_GetUID_Word0(void)
{
  return (uint32_t)(((*((uint32_t *)(0x1FFF7590UL)))));
}




 
static __inline uint32_t LL_GetUID_Word1(void)
{
  return (uint32_t)(((*((uint32_t *)((0x1FFF7590UL) + 4U)))));
}




 
static __inline uint32_t LL_GetUID_Word2(void)
{
  return (uint32_t)(((*((uint32_t *)((0x1FFF7590UL) + 8U)))));
}






 
static __inline uint32_t LL_GetFlashSize(void)
{
  return (uint32_t)(((*((uint32_t *)(0x1FFF75E0UL)))) & 0x0000FFFFUL);
}

















 
static __inline uint32_t LL_GetPackageType(void)
{
  return (uint32_t)(((*((uint32_t *)(0x1FFF7500UL)))) & 0x1FU);
}



 



 








 
static __inline void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
{
   
  ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->LOAD  = (uint32_t)((HCLKFrequency / Ticks) - 1UL);   
  ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->VAL   = 0UL;                                        
  ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->CTRL  = (1UL << 2U) |
                   (1UL );                    
}

void        LL_Init1msTick(uint32_t HCLKFrequency);
void        LL_mDelay(uint32_t Delay);



 



 

void        LL_SetSystemCoreClock(uint32_t HCLKFrequency);
ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency);
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
                                         LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);



 



 



 



 







#line 43 "../Core/Inc/main.h"
#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h"
















 

 







 
#line 29 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h"



 





 

 
 

 

 

 
 


 




 
#line 64 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h"


 




 
#line 95 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h"


 



 




 



 






 



 
#line 134 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h"


 



 
#line 149 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h"


 



 







 



 




 



 
#line 184 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h"


 



 
#line 207 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h"


 



 

 


 



 






 






 



 



 


 


 



 





 
static __inline void LL_PWR_EnableLowPowerRunMode(void)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR1) |= ((0x1UL << (14U))));
}





 
static __inline void LL_PWR_DisableLowPowerRunMode(void)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR1) &= ~((0x1UL << (14U))));
}





 
static __inline uint32_t LL_PWR_IsEnabledLowPowerRunMode(void)
{
  uint32_t temp;
  temp = ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR1) & ((0x1UL << (14U))));

  return ((temp == ((0x1UL << (14U))))?1U:0U);

}





 
static __inline void LL_PWR_EnterLowPowerRunMode(void)
{
  LL_PWR_EnableLowPowerRunMode();
}





 
static __inline void LL_PWR_ExitLowPowerRunMode(void)
{
  LL_PWR_DisableLowPowerRunMode();
}








 
static __inline void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
{
  (((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR1)) = ((((((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR1))) & (~((0x3UL << (9U))))) | (VoltageScaling))));
}







 
static __inline uint32_t LL_PWR_GetRegulVoltageScaling(void)
{
  return (uint32_t)(((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR1) & ((0x3UL << (9U)))));
}






 
static __inline void LL_PWR_EnableRange1BoostMode(void)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR5) &= ~((0x1U << (8U))));
}





 
static __inline void LL_PWR_DisableRange1BoostMode(void)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR5) |= ((0x1U << (8U))));
}





 
static __inline uint32_t LL_PWR_IsEnabledRange1BoostMode(void)
{
  uint32_t temp;
  temp = ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR5) & ((0x1U << (8U))));

  return ((temp == (0U))?1U:0U);
}






 
static __inline void LL_PWR_EnableBkUpAccess(void)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR1) |= ((0x1UL << (8U))));
}





 
static __inline void LL_PWR_DisableBkUpAccess(void)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR1) &= ~((0x1UL << (8U))));
}





 
static __inline uint32_t LL_PWR_IsEnabledBkUpAccess(void)
{
  uint32_t temp;
  temp = ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR1) & ((0x1UL << (8U))));

  return ((temp == ((0x1UL << (8U))))?1U:0U);

}










 
static __inline void LL_PWR_SetPowerMode(uint32_t LowPowerMode)
{
  (((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR1)) = ((((((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR1))) & (~((0x7UL << (0U))))) | (LowPowerMode))));
}









 
static __inline uint32_t LL_PWR_GetPowerMode(void)
{
  return (uint32_t)(((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR1) & ((0x7UL << (0U)))));
}







 
static __inline void LL_PWR_EnableUCPDStandbyMode(void)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR3) |= ((0x1UL << (13U))));
}







 
static __inline void LL_PWR_DisableUCPDStandbyMode(void)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR3) &= ~((0x1UL << (13U))));
}





 
static __inline uint32_t LL_PWR_IsEnabledUCPDStandbyMode(void)
{

  return ((((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR3) & ((0x1UL << (13U)))) == ((0x1UL << (13U)))) ? 1UL : 0UL);

}












 
static __inline void LL_PWR_EnableUCPDDeadBattery(void)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR3) &= ~((0x1UL << (14U))));
}










 
static __inline void LL_PWR_DisableUCPDDeadBattery(void)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR3) |= ((0x1UL << (14U))));
}










 
static __inline uint32_t LL_PWR_IsEnabledUCPDDeadBattery(void)
{
  return ((((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR3) & ((0x1UL << (14U)))) == ((0x1UL << (14U)))) ? 0UL : 1UL);
}


#line 552 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h"

#line 588 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h"















 
static __inline void LL_PWR_EnablePVM(uint32_t PeriphVoltage)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR2) |= (PeriphVoltage));
}















 
static __inline void LL_PWR_DisablePVM(uint32_t PeriphVoltage)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR2) &= ~(PeriphVoltage));
}















 
static __inline uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)
{
  uint32_t temp;
  temp = ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR2) & (PeriphVoltage));

  return ((temp == (PeriphVoltage))?1U:0U);

}














 
static __inline void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
{
  (((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR2)) = ((((((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR2))) & (~((0x7UL << (1U))))) | (PVDLevel))));
}













 
static __inline uint32_t LL_PWR_GetPVDLevel(void)
{
  return (uint32_t)(((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR2) & ((0x7UL << (1U)))));
}





 
static __inline void LL_PWR_EnablePVD(void)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR2) |= ((0x1UL << (0U))));
}





 
static __inline void LL_PWR_DisablePVD(void)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR2) &= ~((0x1UL << (0U))));
}





 
static __inline uint32_t LL_PWR_IsEnabledPVD(void)
{
  uint32_t temp;
  temp = ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR2) & ((0x1UL << (0U))));

  return ((temp == ((0x1UL << (0U))))?1U:0U);
}





 
static __inline void LL_PWR_EnableInternWU(void)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR3) |= ((0x1UL << (15U))));
}





 
static __inline void LL_PWR_DisableInternWU(void)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR3) &= ~((0x1UL << (15U))));
}





 
static __inline uint32_t LL_PWR_IsEnabledInternWU(void)
{
  return ((((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR3) & ((0x1UL << (15U)))) == ((0x1UL << (15U))))?1UL:0UL);
}





 
static __inline void LL_PWR_EnablePUPDCfg(void)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR3) |= ((0x1UL << (10U))));
}





 
static __inline void LL_PWR_DisablePUPDCfg(void)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR3) &= ~((0x1UL << (10U))));
}





 
static __inline uint32_t LL_PWR_IsEnabledPUPDCfg(void)
{
  uint32_t temp;
  temp = ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR3) & ((0x1UL << (10U))));

  return ((temp == ((0x1UL << (10U))))?1U:0U);
}





 
static __inline void LL_PWR_EnableSRAM2Retention(void)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR3) |= ((0x1UL << (8U))));
}





 
static __inline void LL_PWR_DisableSRAM2Retention(void)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR3) &= ~((0x1UL << (8U))));
}





 
static __inline uint32_t LL_PWR_IsEnabledSRAM2Retention(void)
{
  uint32_t temp;
  temp = ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR3) & ((0x1UL << (8U))));

  return ((temp == ((0x1UL << (8U))))?1U:0U);
}















 
static __inline void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR3) |= (WakeUpPin));
}















 
static __inline void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR3) &= ~(WakeUpPin));
}















 
static __inline uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
{
  uint32_t temp;
  temp = ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR3) & (WakeUpPin));

  return ((temp == (WakeUpPin))?1U:0U);
}








 
static __inline void LL_PWR_SetBattChargResistor(uint32_t Resistor)
{
  (((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR4)) = ((((((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR4))) & (~((0x1UL << (9U))))) | (Resistor))));
}







 
static __inline uint32_t LL_PWR_GetBattChargResistor(void)
{
  return (uint32_t)(((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR4) & ((0x1UL << (9U)))));
}





 
static __inline void LL_PWR_EnableBatteryCharging(void)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR4) |= ((0x1UL << (8U))));
}





 
static __inline void LL_PWR_DisableBatteryCharging(void)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR4) &= ~((0x1UL << (8U))));
}





 
static __inline uint32_t LL_PWR_IsEnabledBatteryCharging(void)
{
  uint32_t temp;
  temp = ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR4) & ((0x1UL << (8U))));

  return ((temp == ((0x1UL << (8U))))?1U:0U);
}















 
static __inline void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR4) |= (WakeUpPin));
}















 
static __inline void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR4) &= ~(WakeUpPin));
}















 
static __inline uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
{
  uint32_t temp;
  temp = ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->CR4) & (WakeUpPin));

  return ((temp == (WakeUpPin))?1U:0U);
}






































 
static __inline void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
{
  ((*((volatile uint32_t *)GPIO)) |= (GPIONumber));
}






































 
static __inline void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
{
  ((*((volatile uint32_t *)GPIO)) &= ~(GPIONumber));
}






































 
static __inline uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
{
  return ((((*((volatile uint32_t *)GPIO)) & (GPIONumber)) == (GPIONumber)) ? 1UL : 0UL);
}






































 
static __inline void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
{
  ((*((volatile uint32_t *)(GPIO + 4U))) |= (GPIONumber));
}






































 
static __inline void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
{
  ((*((volatile uint32_t *)(GPIO + 4U))) &= ~(GPIONumber));
}






































 
static __inline uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
{
  return ((((*((volatile uint32_t *)(GPIO + 4U))) & (GPIONumber)) == (GPIONumber)) ? 1UL : 0UL);
}



 



 





 
static __inline uint32_t LL_PWR_IsActiveFlag_InternWU(void)
{
  uint32_t temp;
  temp = ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->SR1) & ((0x1UL << (15U))));

  return ((temp == ((0x1UL << (15U))))?1U:0U);

}





 
static __inline uint32_t LL_PWR_IsActiveFlag_SB(void)
{
  uint32_t temp;
  temp = ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->SR1) & ((0x1UL << (8U))));

  return ((temp == ((0x1UL << (8U))))?1U:0U);

}





 
static __inline uint32_t LL_PWR_IsActiveFlag_WU5(void)
{
  uint32_t temp;
  temp = ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->SR1) & ((0x1UL << (4U))));

  return ((temp == ((0x1UL << (4U))))?1U:0U);
}





 
static __inline uint32_t LL_PWR_IsActiveFlag_WU4(void)
{
  uint32_t temp;
  temp = ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->SR1) & ((0x1UL << (3U))));

  return ((temp == ((0x1UL << (3U))))?1U:0U);
}





 
static __inline uint32_t LL_PWR_IsActiveFlag_WU3(void)
{
  uint32_t temp;
  temp = ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->SR1) & ((0x1UL << (2U))));

  return ((temp == ((0x1UL << (2U))))?1U:0U);
}





 
static __inline uint32_t LL_PWR_IsActiveFlag_WU2(void)
{
  uint32_t temp;
  temp = ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->SR1) & ((0x1UL << (1U))));

  return ((temp == ((0x1UL << (1U))))?1U:0U);
}





 
static __inline uint32_t LL_PWR_IsActiveFlag_WU1(void)
{
  uint32_t temp;
  temp = ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->SR1) & ((0x1UL << (0U))));

  return ((temp == ((0x1UL << (0U))))?1U:0U);
}





 
static __inline void LL_PWR_ClearFlag_SB(void)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->SCR) = ((0x1UL << (8U))));
}





 
static __inline void LL_PWR_ClearFlag_WU(void)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->SCR) = ((0x1FUL << (0U))));
}





 
static __inline void LL_PWR_ClearFlag_WU5(void)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->SCR) = ((0x1UL << (4U))));
}





 
static __inline void LL_PWR_ClearFlag_WU4(void)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->SCR) = ((0x1UL << (3U))));
}





 
static __inline void LL_PWR_ClearFlag_WU3(void)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->SCR) = ((0x1UL << (2U))));
}





 
static __inline void LL_PWR_ClearFlag_WU2(void)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->SCR) = ((0x1UL << (1U))));
}





 
static __inline void LL_PWR_ClearFlag_WU1(void)
{
  ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->SCR) = ((0x1UL << (0U))));
}





 
static __inline uint32_t LL_PWR_IsActiveFlag_PVMO4(void)
{
  uint32_t temp;
  temp = ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->SR2) & ((0x1UL << (15U))));

  return ((temp == ((0x1UL << (15U))))?1U:0U);

}





 
static __inline uint32_t LL_PWR_IsActiveFlag_PVMO3(void)
{
  uint32_t temp;
  temp = ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->SR2) & ((0x1UL << (14U))));

  return ((temp == ((0x1UL << (14U))))?1U:0U);

}






 
static __inline uint32_t LL_PWR_IsActiveFlag_PVMO2(void)
{
  uint32_t temp;
  temp = ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->SR2) & ((0x1UL << (13U))));

  return ((temp == ((0x1UL << (13U))))?1U:0U);

}







 
static __inline uint32_t LL_PWR_IsActiveFlag_PVMO1(void)
{
  uint32_t temp;
  temp = ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->SR2) & ((0x1UL << (12U))));

  return ((temp == ((0x1UL << (12U))))?1U:0U);

}






 
static __inline uint32_t LL_PWR_IsActiveFlag_PVDO(void)
{
 uint32_t temp;
 temp = ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->SR2) & ((0x1UL << (11U))));

 return ((temp == ((0x1UL << (11U))))?1U:0U);

}





 
static __inline uint32_t LL_PWR_IsActiveFlag_VOS(void)
{
  uint32_t temp;
  temp = ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->SR2) & ((0x1UL << (10U))));

  return ((temp == ((0x1UL << (10U))))?1U:0U);

}






 
static __inline uint32_t LL_PWR_IsActiveFlag_REGLPF(void)
{
  uint32_t temp;
  temp = ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->SR2) & ((0x1UL << (9U))));

  return ((temp == ((0x1UL << (9U))))?1U:0U);

}





 
static __inline uint32_t LL_PWR_IsActiveFlag_REGLPS(void)
{
  uint32_t temp;
  temp = ((((PWR_TypeDef *) ((0x40000000UL) + 0x7000UL))->SR2) & ((0x1UL << (8U))));

  return ((temp == ((0x1UL << (8U))))?1U:0U);

}



 




 
ErrorStatus LL_PWR_DeInit(void);


 




 
 
 
#line 1579 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h"


 



 



 





 







#line 44 "../Core/Inc/main.h"
#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_spi.h"
















 

 







 
#line 29 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_spi.h"



 





 

 
 
 

 



 



 
typedef struct
{
  uint32_t TransferDirection;       


 

  uint32_t Mode;                    


 

  uint32_t DataWidth;               


 

  uint32_t ClockPolarity;           


 

  uint32_t ClockPhase;              


 

  uint32_t NSS;                     


 

  uint32_t BaudRate;                



 

  uint32_t BitOrder;                


 

  uint32_t CRCCalculation;          


 

  uint32_t CRCPoly;                 


 

} LL_SPI_InitTypeDef;



 


 


 




 
#line 129 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_spi.h"


 




 





 



 




 



 




 



 




 



 




 



 
#line 191 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_spi.h"


 



 




 



 






 



 





 



 
#line 241 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_spi.h"


 




 




 




 




 



 




 



 






 



 






 



 





 



 

 


 



 







 







 



 



 

 


 



 






 
static __inline void LL_SPI_Enable(SPI_TypeDef *SPIx)
{
  ((SPIx->CR1) |= ((0x1UL << (6U))));
}







 
static __inline void LL_SPI_Disable(SPI_TypeDef *SPIx)
{
  ((SPIx->CR1) &= ~((0x1UL << (6U))));
}






 
static __inline uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
{
  return ((((SPIx->CR1) & ((0x1UL << (6U)))) == ((0x1UL << (6U)))) ? 1UL : 0UL);
}











 
static __inline void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
{
  (((SPIx->CR1)) = ((((((SPIx->CR1))) & (~((0x1UL << (2U)) | (0x1UL << (8U))))) | (Mode))));
}









 
static __inline uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
{
  return (uint32_t)(((SPIx->CR1) & ((0x1UL << (2U)) | (0x1UL << (8U)))));
}










 
static __inline void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
{
  (((SPIx->CR2)) = ((((((SPIx->CR2))) & (~((0x1UL << (4U))))) | (Standard))));
}








 
static __inline uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
{
  return (uint32_t)(((SPIx->CR2) & ((0x1UL << (4U)))));
}











 
static __inline void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
{
  (((SPIx->CR1)) = ((((((SPIx->CR1))) & (~((0x1UL << (0U))))) | (ClockPhase))));
}








 
static __inline uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
{
  return (uint32_t)(((SPIx->CR1) & ((0x1UL << (0U)))));
}











 
static __inline void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
{
  (((SPIx->CR1)) = ((((((SPIx->CR1))) & (~((0x1UL << (1U))))) | (ClockPolarity))));
}








 
static __inline uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
{
  return (uint32_t)(((SPIx->CR1) & ((0x1UL << (1U)))));
}
















 
static __inline void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
{
  (((SPIx->CR1)) = ((((((SPIx->CR1))) & (~((0x7UL << (3U))))) | (BaudRate))));
}














 
static __inline uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
{
  return (uint32_t)(((SPIx->CR1) & ((0x7UL << (3U)))));
}










 
static __inline void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
{
  (((SPIx->CR1)) = ((((((SPIx->CR1))) & (~((0x1UL << (7U))))) | (BitOrder))));
}








 
static __inline uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
{
  return (uint32_t)(((SPIx->CR1) & ((0x1UL << (7U)))));
}















 
static __inline void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
{
  (((SPIx->CR1)) = ((((((SPIx->CR1))) & (~((0x1UL << (10U)) | (0x1UL << (15U)) | (0x1UL << (14U))))) | (TransferDirection))));
}












 
static __inline uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
{
  return (uint32_t)(((SPIx->CR1) & ((0x1UL << (10U)) | (0x1UL << (15U)) | (0x1UL << (14U)))));
}




















 
static __inline void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
{
  (((SPIx->CR2)) = ((((((SPIx->CR2))) & (~((0xFUL << (8U))))) | (DataWidth))));
}



















 
static __inline uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
{
  return (uint32_t)(((SPIx->CR2) & ((0xFUL << (8U)))));
}









 
static __inline void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
{
  (((SPIx->CR2)) = ((((((SPIx->CR2))) & (~((0x1UL << (12U))))) | (Threshold))));
}








 
static __inline uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
{
  return (uint32_t)(((SPIx->CR2) & ((0x1UL << (12U)))));
}



 



 







 
static __inline void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
{
  ((SPIx->CR1) |= ((0x1UL << (13U))));
}







 
static __inline void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
{
  ((SPIx->CR1) &= ~((0x1UL << (13U))));
}







 
static __inline uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
{
  return ((((SPIx->CR1) & ((0x1UL << (13U)))) == ((0x1UL << (13U)))) ? 1UL : 0UL);
}










 
static __inline void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
{
  (((SPIx->CR1)) = ((((((SPIx->CR1))) & (~((0x1UL << (11U))))) | (CRCLength))));
}








 
static __inline uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
{
  return (uint32_t)(((SPIx->CR1) & ((0x1UL << (11U)))));
}







 
static __inline void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
{
  ((SPIx->CR1) |= ((0x1UL << (12U))));
}







 
static __inline void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
{
  ((SPIx->CRCPR) = ((uint16_t)CRCPoly));
}






 
static __inline uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
{
  return (uint32_t)(((SPIx->CRCPR)));
}






 
static __inline uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
{
  return (uint32_t)(((SPIx->RXCRCR)));
}






 
static __inline uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
{
  return (uint32_t)(((SPIx->TXCRCR)));
}



 



 












 
static __inline void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
{
  (((SPIx->CR1)) = ((((((SPIx->CR1))) & (~((0x1UL << (9U))))) | (NSS))));
  (((SPIx->CR2)) = ((((((SPIx->CR2))) & (~((0x1UL << (2U))))) | (((uint32_t)(NSS >> 16U))))));
}










 
static __inline uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
{
  uint32_t Ssm  = (((SPIx->CR1) & ((0x1UL << (9U)))));
  uint32_t Ssoe = (((SPIx->CR2) & ((0x1UL << (2U)))) << 16U);
  return (Ssm | Ssoe);
}







 
static __inline void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
{
  ((SPIx->CR2) |= ((0x1UL << (3U))));
}







 
static __inline void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
{
  ((SPIx->CR2) &= ~((0x1UL << (3U))));
}







 
static __inline uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
{
  return ((((SPIx->CR2) & ((0x1UL << (3U)))) == ((0x1UL << (3U)))) ? 1UL : 0UL);
}



 



 






 
static __inline uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
{
  return ((((SPIx->SR) & ((0x1UL << (0U)))) == ((0x1UL << (0U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
{
  return ((((SPIx->SR) & ((0x1UL << (1U)))) == ((0x1UL << (1U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
{
  return ((((SPIx->SR) & ((0x1UL << (4U)))) == ((0x1UL << (4U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
{
  return ((((SPIx->SR) & ((0x1UL << (5U)))) == ((0x1UL << (5U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
{
  return ((((SPIx->SR) & ((0x1UL << (6U)))) == ((0x1UL << (6U)))) ? 1UL : 0UL);
}













 
static __inline uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
{
  return ((((SPIx->SR) & ((0x1UL << (7U)))) == ((0x1UL << (7U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
{
  return ((((SPIx->SR) & ((0x1UL << (8U)))) == ((0x1UL << (8U)))) ? 1UL : 0UL);
}










 
static __inline uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
{
  return (uint32_t)(((SPIx->SR) & ((0x3UL << (9U)))));
}










 
static __inline uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
{
  return (uint32_t)(((SPIx->SR) & ((0x3UL << (11U)))));
}






 
static __inline void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
{
  ((SPIx->SR) &= ~((0x1UL << (4U))));
}








 
static __inline void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
{
  volatile uint32_t tmpreg_sr;
  tmpreg_sr = SPIx->SR;
  (void) tmpreg_sr;
  ((SPIx->CR1) &= ~((0x1UL << (6U))));
}








 
static __inline void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
{
  volatile uint32_t tmpreg;
  tmpreg = SPIx->DR;
  (void) tmpreg;
  tmpreg = SPIx->SR;
  (void) tmpreg;
}







 
static __inline void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
{
  volatile uint32_t tmpreg;
  tmpreg = SPIx->SR;
  (void) tmpreg;
}



 



 







 
static __inline void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
{
  ((SPIx->CR2) |= ((0x1UL << (5U))));
}






 
static __inline void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
{
  ((SPIx->CR2) |= ((0x1UL << (6U))));
}






 
static __inline void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
{
  ((SPIx->CR2) |= ((0x1UL << (7U))));
}







 
static __inline void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
{
  ((SPIx->CR2) &= ~((0x1UL << (5U))));
}






 
static __inline void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
{
  ((SPIx->CR2) &= ~((0x1UL << (6U))));
}






 
static __inline void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
{
  ((SPIx->CR2) &= ~((0x1UL << (7U))));
}






 
static __inline uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
{
  return ((((SPIx->CR2) & ((0x1UL << (5U)))) == ((0x1UL << (5U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
{
  return ((((SPIx->CR2) & ((0x1UL << (6U)))) == ((0x1UL << (6U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
{
  return ((((SPIx->CR2) & ((0x1UL << (7U)))) == ((0x1UL << (7U)))) ? 1UL : 0UL);
}



 



 






 
static __inline void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
{
  ((SPIx->CR2) |= ((0x1UL << (0U))));
}






 
static __inline void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
{
  ((SPIx->CR2) &= ~((0x1UL << (0U))));
}






 
static __inline uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
{
  return ((((SPIx->CR2) & ((0x1UL << (0U)))) == ((0x1UL << (0U)))) ? 1UL : 0UL);
}






 
static __inline void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
{
  ((SPIx->CR2) |= ((0x1UL << (1U))));
}






 
static __inline void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
{
  ((SPIx->CR2) &= ~((0x1UL << (1U))));
}






 
static __inline uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
{
  return ((((SPIx->CR2) & ((0x1UL << (1U)))) == ((0x1UL << (1U)))) ? 1UL : 0UL);
}









 
static __inline void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
{
  (((SPIx->CR2)) = ((((((SPIx->CR2))) & (~((0x1UL << (13U))))) | ((Parity << (13U))))));
}








 
static __inline uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
{
  return (uint32_t)(((SPIx->CR2) & ((0x1UL << (13U)))) >> (13U));
}









 
static __inline void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
{
  (((SPIx->CR2)) = ((((((SPIx->CR2))) & (~((0x1UL << (14U))))) | ((Parity << (14U))))));
}








 
static __inline uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
{
  return (uint32_t)(((SPIx->CR2) & ((0x1UL << (14U)))) >> (14U));
}






 
static __inline uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
{
  return (uint32_t) &(SPIx->DR);
}



 



 






 
static __inline uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
{
  return (*((volatile uint8_t *)&SPIx->DR));
}






 
static __inline uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
{
  return (uint16_t)(((SPIx->DR)));
}







 
static __inline void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
{




  *((volatile uint8_t *)&SPIx->DR) = TxData;

}







 
static __inline void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
{




  SPIx->DR = TxData;

}



 



 

ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
void        LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);



 



 



 




 

 
 
 

 



 



 

typedef struct
{
  uint32_t Mode;                    


 

  uint32_t Standard;                


 


  uint32_t DataFormat;              


 


  uint32_t MCLKOutput;              


 


  uint32_t AudioFreq;               



 


  uint32_t ClockPolarity;           


 

} LL_I2S_InitTypeDef;



 


 


 




 
#line 1485 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_spi.h"


 




 





 



 






 



 




 



 







 



 






 



 




 





 




 



 

#line 1577 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_spi.h"


 




 

 


 



 







 







 



 



 


 



 



 







 
static __inline void LL_I2S_Enable(SPI_TypeDef *SPIx)
{
  ((SPIx->I2SCFGR) |= ((0x1UL << (11U)) | (0x1UL << (10U))));
}






 
static __inline void LL_I2S_Disable(SPI_TypeDef *SPIx)
{
  ((SPIx->I2SCFGR) &= ~((0x1UL << (11U)) | (0x1UL << (10U))));
}






 
static __inline uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
{
  return ((((SPIx->I2SCFGR) & ((0x1UL << (10U)))) == ((0x1UL << (10U)))) ? 1UL : 0UL);
}












 
static __inline void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
{
  (((SPIx->I2SCFGR)) = ((((((SPIx->I2SCFGR))) & (~((0x3UL << (1U)) | (0x1UL << (0U))))) | (DataFormat))));
}











 
static __inline uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
{
  return (uint32_t)(((SPIx->I2SCFGR) & ((0x3UL << (1U)) | (0x1UL << (0U)))));
}









 
static __inline void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
{
  ((SPIx->I2SCFGR) |= (ClockPolarity));
}








 
static __inline uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
{
  return (uint32_t)(((SPIx->I2SCFGR) & ((0x1UL << (3U)))));
}













 
static __inline void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
{
  (((SPIx->I2SCFGR)) = ((((((SPIx->I2SCFGR))) & (~((0x3UL << (4U)) | (0x1UL << (7U))))) | (Standard))));
}












 
static __inline uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
{
  return (uint32_t)(((SPIx->I2SCFGR) & ((0x3UL << (4U)) | (0x1UL << (7U)))));
}











 
static __inline void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
{
  (((SPIx->I2SCFGR)) = ((((((SPIx->I2SCFGR))) & (~((0x3UL << (8U))))) | (Mode))));
}










 
static __inline uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
{
  return (uint32_t)(((SPIx->I2SCFGR) & ((0x3UL << (8U)))));
}







 
static __inline void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
{
  (((SPIx->I2SPR)) = ((((((SPIx->I2SPR))) & (~((0xFFUL << (0U))))) | (PrescalerLinear))));
}






 
static __inline uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
{
  return (uint32_t)(((SPIx->I2SPR) & ((0xFFUL << (0U)))));
}









 
static __inline void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
{
  (((SPIx->I2SPR)) = ((((((SPIx->I2SPR))) & (~((0x1UL << (8U))))) | (PrescalerParity << 8U))));
}








 
static __inline uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
{
  return (uint32_t)(((SPIx->I2SPR) & ((0x1UL << (8U)))) >> 8U);
}






 
static __inline void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
{
  ((SPIx->I2SPR) |= ((0x1UL << (9U))));
}






 
static __inline void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
{
  ((SPIx->I2SPR) &= ~((0x1UL << (9U))));
}






 
static __inline uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
{
  return ((((SPIx->I2SPR) & ((0x1UL << (9U)))) == ((0x1UL << (9U)))) ? 1UL : 0UL);
}







 
static __inline void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx)
{
  ((SPIx->I2SCFGR) |= ((0x1UL << (12U))));
}






 
static __inline void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
{
  ((SPIx->I2SCFGR) &= ~((0x1UL << (12U))));
}






 
static __inline uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
{
  return ((((SPIx->I2SCFGR) & ((0x1UL << (12U)))) == ((0x1UL << (12U)))) ? 1UL : 0UL);
}




 



 






 
static __inline uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
{
  return LL_SPI_IsActiveFlag_RXNE(SPIx);
}






 
static __inline uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
{
  return LL_SPI_IsActiveFlag_TXE(SPIx);
}






 
static __inline uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
{
  return LL_SPI_IsActiveFlag_BSY(SPIx);
}






 
static __inline uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
{
  return LL_SPI_IsActiveFlag_OVR(SPIx);
}






 
static __inline uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
{
  return ((((SPIx->SR) & ((0x1UL << (3U)))) == ((0x1UL << (3U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
{
  return LL_SPI_IsActiveFlag_FRE(SPIx);
}









 
static __inline uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
{
  return ((((SPIx->SR) & ((0x1UL << (2U)))) == ((0x1UL << (2U)))) ? 1UL : 0UL);
}






 
static __inline void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
{
  LL_SPI_ClearFlag_OVR(SPIx);
}






 
static __inline void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
{
  volatile uint32_t tmpreg;
  tmpreg = SPIx->SR;
  (void)tmpreg;
}






 
static __inline void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
{
  LL_SPI_ClearFlag_FRE(SPIx);
}



 



 







 
static __inline void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
{
  LL_SPI_EnableIT_ERR(SPIx);
}






 
static __inline void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
{
  LL_SPI_EnableIT_RXNE(SPIx);
}






 
static __inline void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
{
  LL_SPI_EnableIT_TXE(SPIx);
}







 
static __inline void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
{
  LL_SPI_DisableIT_ERR(SPIx);
}






 
static __inline void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
{
  LL_SPI_DisableIT_RXNE(SPIx);
}






 
static __inline void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
{
  LL_SPI_DisableIT_TXE(SPIx);
}






 
static __inline uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
{
  return LL_SPI_IsEnabledIT_ERR(SPIx);
}






 
static __inline uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
{
  return LL_SPI_IsEnabledIT_RXNE(SPIx);
}






 
static __inline uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
{
  return LL_SPI_IsEnabledIT_TXE(SPIx);
}



 



 






 
static __inline void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
{
  LL_SPI_EnableDMAReq_RX(SPIx);
}






 
static __inline void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
{
  LL_SPI_DisableDMAReq_RX(SPIx);
}






 
static __inline uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
{
  return LL_SPI_IsEnabledDMAReq_RX(SPIx);
}






 
static __inline void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
{
  LL_SPI_EnableDMAReq_TX(SPIx);
}






 
static __inline void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
{
  LL_SPI_DisableDMAReq_TX(SPIx);
}






 
static __inline uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
{
  return LL_SPI_IsEnabledDMAReq_TX(SPIx);
}



 



 






 
static __inline uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
{
  return LL_SPI_ReceiveData16(SPIx);
}







 
static __inline void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
{
  LL_SPI_TransmitData16(SPIx, TxData);
}



 




 

ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
void        LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
void        LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);



 




 



 






 







#line 45 "../Core/Inc/main.h"
#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"
















 

 







 
#line 29 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"



 





 

 
 


 
static const uint8_t OFFSET_TAB_CCMRx[] =
{
  0x00U,    
  0x00U,    
  0x00U,    
  0x00U,    
  0x04U,    
  0x04U,    
  0x04U,    
  0x04U,    
  0x38U,    
  0x38U     

};

static const uint8_t SHIFT_TAB_OCxx[] =
{
  0U,             
  0U,             
  8U,             
  0U,             
  0U,             
  0U,             
  8U,             
  0U,             
  0U,             
  8U              
};

static const uint8_t SHIFT_TAB_ICxx[] =
{
  0U,             
  0U,             
  8U,             
  0U,             
  0U,             
  0U,             
  8U,             
  0U,             
  0U,             
  0U              
};

static const uint8_t SHIFT_TAB_CCxP[] =
{
  0U,             
  2U,             
  4U,             
  6U,             
  8U,             
  10U,            
  12U,            
  14U,            
  16U,            
  20U             
};

static const uint8_t SHIFT_TAB_OISx[] =
{
  0U,             
  1U,             
  2U,             
  3U,             
  4U,             
  5U,             
  6U,             
  7U,             
  8U,             
  10U             
};


 

 


 

 


 




 





 







 


 





 

 


 













 
#line 185 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"








 






 


 



 



 
typedef struct
{
  uint16_t Prescaler;         



 

  uint32_t CounterMode;       



 

  uint32_t Autoreload;        






 

  uint32_t ClockDivision;     



 

  uint32_t RepetitionCounter;  











 
} LL_TIM_InitTypeDef;



 
typedef struct
{
  uint32_t OCMode;        



 

  uint32_t OCState;       



 

  uint32_t OCNState;      



 

  uint32_t CompareValue;  



 

  uint32_t OCPolarity;    



 

  uint32_t OCNPolarity;   



 


  uint32_t OCIdleState;   



 

  uint32_t OCNIdleState;  



 
} LL_TIM_OC_InitTypeDef;



 

typedef struct
{

  uint32_t ICPolarity;    



 

  uint32_t ICActiveInput; 



 

  uint32_t ICPrescaler;   



 

  uint32_t ICFilter;      



 
} LL_TIM_IC_InitTypeDef;




 
typedef struct
{
  uint32_t EncoderMode;     



 

  uint32_t IC1Polarity;     



 

  uint32_t IC1ActiveInput;  



 

  uint32_t IC1Prescaler;    



 

  uint32_t IC1Filter;       



 

  uint32_t IC2Polarity;      



 

  uint32_t IC2ActiveInput;  



 

  uint32_t IC2Prescaler;    



 

  uint32_t IC2Filter;       



 

} LL_TIM_ENCODER_InitTypeDef;



 
typedef struct
{

  uint32_t IC1Polarity;        



 

  uint32_t IC1Prescaler;       





 

  uint32_t IC1Filter;          




 

  uint32_t CommutationDelay;   





 
} LL_TIM_HALLSENSOR_InitTypeDef;



 
typedef struct
{
  uint32_t OSSRState;            






 

  uint32_t OSSIState;            






 

  uint32_t LockLevel;            



 

  uint8_t DeadTime;              







 

  uint16_t BreakState;           






 

  uint32_t BreakPolarity;        






 

  uint32_t BreakFilter;          






 

  uint32_t BreakAFMode;           








 

  uint32_t Break2State;          






 

  uint32_t Break2Polarity;        






 

  uint32_t Break2Filter;          






 

  uint32_t Break2AFMode;          








 

  uint32_t AutomaticOutput;      






 
} LL_TIM_BDTR_InitTypeDef;



 


 


 




 
#line 600 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 




 




 



 




 



 




 





 
#line 649 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 



 




 



 




 



 







 



 





 



 




 



 




 



 




 



 






 



 
#line 744 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 




 




 




 
#line 778 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 



 




 



 




 



 






 



 





 



 






 



 
#line 851 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 



 





 



 





 



 
#line 887 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 



 
#line 903 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 



 
#line 926 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 



 
#line 940 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 



 




 



 
#line 972 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 



 




 



 






 



 
#line 1015 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 



 
#line 1044 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 



 
#line 1071 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 



 
#line 1097 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 



 
#line 1122 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 




 
#line 1146 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 




 
#line 1176 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 




 
#line 1208 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 




 




 



 
#line 1241 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 



 




 



 
#line 1273 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 



 




 



 




 



 




 



 
#line 1321 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 



 




 



 




 



 




 



 
#line 1382 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 



 
#line 1415 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 



 







 



 
#line 1442 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 



 
#line 1457 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 



 




 



 





 



 
#line 1497 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 



 
#line 1518 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 



 




 



 
#line 1548 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 



 
#line 1569 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 



 






 



 






 




 
#line 1616 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 



 
#line 1637 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 




 







 



 
#line 1667 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 



 
#line 1683 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 



 
#line 1699 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 



 
#line 1715 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 




 







 




 
#line 1750 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 



 





 



 
#line 1773 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 



 




 


 
#line 1796 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"


 



 




 



 



 


 

 


 



 






 







 



 



 








 













 
#line 1887 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h"







 










 











 












 












 













 













 













 






 




 

 


 



 





 
static __inline void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
{
  ((TIMx->CR1) |= ((0x1UL << (0U))));
}






 
static __inline void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
{
  ((TIMx->CR1) &= ~((0x1UL << (0U))));
}






 
static __inline uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
{
  return ((((TIMx->CR1) & ((0x1UL << (0U)))) == ((0x1UL << (0U)))) ? 1UL : 0UL);
}






 
static __inline void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
{
  ((TIMx->CR1) &= ~((0x1UL << (1U))));
}






 
static __inline void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
{
  ((TIMx->CR1) |= ((0x1UL << (1U))));
}






 
static __inline uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
{
  return ((((TIMx->CR1) & ((0x1UL << (1U)))) == (uint32_t)RESET) ? 1UL : 0UL);
}
















 
static __inline void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
{
  (((TIMx->CR1)) = ((((((TIMx->CR1))) & (~((0x1UL << (2U))))) | (UpdateSource))));
}








 
static __inline uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
{
  return (uint32_t)(((TIMx->CR1) & ((0x1UL << (2U)))));
}









 
static __inline void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
{
  (((TIMx->CR1)) = ((((((TIMx->CR1))) & (~((0x1UL << (3U))))) | (OnePulseMode))));
}








 
static __inline uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
{
  return (uint32_t)(((TIMx->CR1) & ((0x1UL << (3U)))));
}



















 
static __inline void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
{
  (((TIMx->CR1)) = ((((((TIMx->CR1))) & (~(((0x1UL << (4U)) | (0x3UL << (5U)))))) | (CounterMode))));
}















 
static __inline uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
{
  uint32_t counter_mode;

  counter_mode = (uint32_t)(((TIMx->CR1) & ((0x3UL << (5U)))));

  if (counter_mode == 0U)
  {
    counter_mode = (uint32_t)(((TIMx->CR1) & ((0x1UL << (4U)))));
  }

  return counter_mode;
}






 
static __inline void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
{
  ((TIMx->CR1) |= ((0x1UL << (7U))));
}






 
static __inline void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
{
  ((TIMx->CR1) &= ~((0x1UL << (7U))));
}






 
static __inline uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
{
  return ((((TIMx->CR1) & ((0x1UL << (7U)))) == ((0x1UL << (7U)))) ? 1UL : 0UL);
}














 
static __inline void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
{
  (((TIMx->CR1)) = ((((((TIMx->CR1))) & (~((0x3UL << (8U))))) | (ClockDivision))));
}













 
static __inline uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
{
  return (uint32_t)(((TIMx->CR1) & ((0x3UL << (8U)))));
}










 
static __inline void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
{
  ((TIMx->CNT) = (Counter));
}









 
static __inline uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
{
  return (uint32_t)(((TIMx->CNT)));
}








 
static __inline uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
{
  return (uint32_t)(((TIMx->CR1) & ((0x1UL << (4U)))));
}











 
static __inline void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
{
  ((TIMx->PSC) = (Prescaler));
}






 
static __inline uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
{
  return (uint32_t)(((TIMx->PSC)));
}













 
static __inline void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
{
  ((TIMx->ARR) = (AutoReload));
}









 
static __inline uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
{
  return (uint32_t)(((TIMx->ARR)));
}










 
static __inline void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
{
  ((TIMx->RCR) = (RepetitionCounter));
}








 
static __inline uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
{
  return (uint32_t)(((TIMx->RCR)));
}








 
static __inline void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
{
  ((TIMx->CR1) |= ((0x1UL << (11U))));
}






 
static __inline void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
{
  ((TIMx->CR1) &= ~((0x1UL << (11U))));
}





 
static __inline uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter)
{
  return (((Counter & (0x1UL << (31U))) == ((0x1UL << (31U)))) ? 1UL : 0UL);
}








 
static __inline void LL_TIM_EnableDithering(TIM_TypeDef *TIMx)
{
  ((TIMx->CR1) |= ((0x1UL << (12U))));
}








 
static __inline void LL_TIM_DisableDithering(TIM_TypeDef *TIMx)
{
  ((TIMx->CR1) &= ~((0x1UL << (12U))));
}








 
static __inline uint32_t LL_TIM_IsEnabledDithering(TIM_TypeDef *TIMx)
{
  return ((((TIMx->CR1) & ((0x1UL << (12U)))) == ((0x1UL << (12U)))) ? 1UL : 0UL);
}



 



 










 
static __inline void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
{
  ((TIMx->CR2) |= ((0x1UL << (0U))));
}








 
static __inline void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
{
  ((TIMx->CR2) &= ~((0x1UL << (0U))));
}











 
static __inline void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
{
  (((TIMx->CR2)) = ((((((TIMx->CR2))) & (~((0x1UL << (2U))))) | (CCUpdateSource))));
}









 
static __inline void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
{
  (((TIMx->CR2)) = ((((((TIMx->CR2))) & (~((0x1UL << (3U))))) | (DMAReqTrigger))));
}








 
static __inline uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
{
  return (uint32_t)(((TIMx->CR2) & ((0x1UL << (3U)))));
}














 
static __inline void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
{
  (((TIMx->BDTR)) = ((((((TIMx->BDTR))) & (~((0x3UL << (8U))))) | (LockLevel))));
}


























 
static __inline void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
{
  ((TIMx->CCER) |= (Channels));
}


























 
static __inline void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
{
  ((TIMx->CCER) &= ~(Channels));
}


























 
static __inline uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
{
  return ((((TIMx->CCER) & (Channels)) == (Channels)) ? 1UL : 0UL);
}



 



 
































 
static __inline void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
{
  uint8_t iChannel = (((Channel) == (0x1UL << (0U))) ? 0U : ((Channel) == (0x1UL << (2U))) ? 1U : ((Channel) == (0x1UL << (4U))) ? 2U : ((Channel) == (0x1UL << (6U))) ? 3U : ((Channel) == (0x1UL << (8U))) ? 4U : ((Channel) == (0x1UL << (10U))) ? 5U : ((Channel) == (0x1UL << (12U))) ? 6U : ((Channel) == (0x1UL << (14U))) ? 7U : ((Channel) == (0x1UL << (16U))) ? 8U : 9U);
  volatile uint32_t *pReg = (volatile uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  ((*pReg) &= ~(((0x3UL << (0U)) << SHIFT_TAB_OCxx[iChannel])));
  (((TIMx->CCER)) = ((((((TIMx->CCER))) & (~(((0x1UL << (1U)) << SHIFT_TAB_CCxP[iChannel])))) | ((Configuration & (0x1UL << (1U))) << SHIFT_TAB_CCxP[iChannel]))));

  (((TIMx->CR2)) = ((((((TIMx->CR2))) & (~(((0x1UL << (8U)) << SHIFT_TAB_OISx[iChannel])))) | ((Configuration & (0x1UL << (8U))) << SHIFT_TAB_OISx[iChannel]))));

}




































 
static __inline void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
{
  uint8_t iChannel = (((Channel) == (0x1UL << (0U))) ? 0U : ((Channel) == (0x1UL << (2U))) ? 1U : ((Channel) == (0x1UL << (4U))) ? 2U : ((Channel) == (0x1UL << (6U))) ? 3U : ((Channel) == (0x1UL << (8U))) ? 4U : ((Channel) == (0x1UL << (10U))) ? 5U : ((Channel) == (0x1UL << (12U))) ? 6U : ((Channel) == (0x1UL << (14U))) ? 7U : ((Channel) == (0x1UL << (16U))) ? 8U : 9U);
  volatile uint32_t *pReg = (volatile uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  (((*pReg)) = ((((((*pReg))) & (~((((0x1007UL << (4U)) | (0x3UL << (0U))) << SHIFT_TAB_OCxx[iChannel])))) | (Mode << SHIFT_TAB_OCxx[iChannel]))));
}


































 
static __inline uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
{
  uint8_t iChannel = (((Channel) == (0x1UL << (0U))) ? 0U : ((Channel) == (0x1UL << (2U))) ? 1U : ((Channel) == (0x1UL << (4U))) ? 2U : ((Channel) == (0x1UL << (6U))) ? 3U : ((Channel) == (0x1UL << (8U))) ? 4U : ((Channel) == (0x1UL << (10U))) ? 5U : ((Channel) == (0x1UL << (12U))) ? 6U : ((Channel) == (0x1UL << (14U))) ? 7U : ((Channel) == (0x1UL << (16U))) ? 8U : 9U);
  const volatile uint32_t *pReg = (volatile uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  return (((*pReg) & ((((0x1007UL << (4U)) | (0x3UL << (0U))) << SHIFT_TAB_OCxx[iChannel]))) >> SHIFT_TAB_OCxx[iChannel]);
}





























 
static __inline void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
{
  uint8_t iChannel = (((Channel) == (0x1UL << (0U))) ? 0U : ((Channel) == (0x1UL << (2U))) ? 1U : ((Channel) == (0x1UL << (4U))) ? 2U : ((Channel) == (0x1UL << (6U))) ? 3U : ((Channel) == (0x1UL << (8U))) ? 4U : ((Channel) == (0x1UL << (10U))) ? 5U : ((Channel) == (0x1UL << (12U))) ? 6U : ((Channel) == (0x1UL << (14U))) ? 7U : ((Channel) == (0x1UL << (16U))) ? 8U : 9U);
  (((TIMx->CCER)) = ((((((TIMx->CCER))) & (~(((0x1UL << (1U)) << SHIFT_TAB_CCxP[iChannel])))) | (Polarity << SHIFT_TAB_CCxP[iChannel]))));
}




























 
static __inline uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
{
  uint8_t iChannel = (((Channel) == (0x1UL << (0U))) ? 0U : ((Channel) == (0x1UL << (2U))) ? 1U : ((Channel) == (0x1UL << (4U))) ? 2U : ((Channel) == (0x1UL << (6U))) ? 3U : ((Channel) == (0x1UL << (8U))) ? 4U : ((Channel) == (0x1UL << (10U))) ? 5U : ((Channel) == (0x1UL << (12U))) ? 6U : ((Channel) == (0x1UL << (14U))) ? 7U : ((Channel) == (0x1UL << (16U))) ? 8U : 9U);
  return (((TIMx->CCER) & (((0x1UL << (1U)) << SHIFT_TAB_CCxP[iChannel]))) >> SHIFT_TAB_CCxP[iChannel]);
}

































 
static __inline void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
{
  uint8_t iChannel = (((Channel) == (0x1UL << (0U))) ? 0U : ((Channel) == (0x1UL << (2U))) ? 1U : ((Channel) == (0x1UL << (4U))) ? 2U : ((Channel) == (0x1UL << (6U))) ? 3U : ((Channel) == (0x1UL << (8U))) ? 4U : ((Channel) == (0x1UL << (10U))) ? 5U : ((Channel) == (0x1UL << (12U))) ? 6U : ((Channel) == (0x1UL << (14U))) ? 7U : ((Channel) == (0x1UL << (16U))) ? 8U : 9U);
  (((TIMx->CR2)) = ((((((TIMx->CR2))) & (~(((0x1UL << (8U)) << SHIFT_TAB_OISx[iChannel])))) | (IdleState << SHIFT_TAB_OISx[iChannel]))));
}




























 
static __inline uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
{
  uint8_t iChannel = (((Channel) == (0x1UL << (0U))) ? 0U : ((Channel) == (0x1UL << (2U))) ? 1U : ((Channel) == (0x1UL << (4U))) ? 2U : ((Channel) == (0x1UL << (6U))) ? 3U : ((Channel) == (0x1UL << (8U))) ? 4U : ((Channel) == (0x1UL << (10U))) ? 5U : ((Channel) == (0x1UL << (12U))) ? 6U : ((Channel) == (0x1UL << (14U))) ? 7U : ((Channel) == (0x1UL << (16U))) ? 8U : 9U);
  return (((TIMx->CR2) & (((0x1UL << (8U)) << SHIFT_TAB_OISx[iChannel]))) >> SHIFT_TAB_OISx[iChannel]);
}



















 
static __inline void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
  uint8_t iChannel = (((Channel) == (0x1UL << (0U))) ? 0U : ((Channel) == (0x1UL << (2U))) ? 1U : ((Channel) == (0x1UL << (4U))) ? 2U : ((Channel) == (0x1UL << (6U))) ? 3U : ((Channel) == (0x1UL << (8U))) ? 4U : ((Channel) == (0x1UL << (10U))) ? 5U : ((Channel) == (0x1UL << (12U))) ? 6U : ((Channel) == (0x1UL << (14U))) ? 7U : ((Channel) == (0x1UL << (16U))) ? 8U : 9U);
  volatile uint32_t *pReg = (volatile uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  ((*pReg) |= (((0x1UL << (2U)) << SHIFT_TAB_OCxx[iChannel])));

}


















 
static __inline void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
  uint8_t iChannel = (((Channel) == (0x1UL << (0U))) ? 0U : ((Channel) == (0x1UL << (2U))) ? 1U : ((Channel) == (0x1UL << (4U))) ? 2U : ((Channel) == (0x1UL << (6U))) ? 3U : ((Channel) == (0x1UL << (8U))) ? 4U : ((Channel) == (0x1UL << (10U))) ? 5U : ((Channel) == (0x1UL << (12U))) ? 6U : ((Channel) == (0x1UL << (14U))) ? 7U : ((Channel) == (0x1UL << (16U))) ? 8U : 9U);
  volatile uint32_t *pReg = (volatile uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  ((*pReg) &= ~(((0x1UL << (2U)) << SHIFT_TAB_OCxx[iChannel])));

}


















 
static __inline uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
  uint8_t iChannel = (((Channel) == (0x1UL << (0U))) ? 0U : ((Channel) == (0x1UL << (2U))) ? 1U : ((Channel) == (0x1UL << (4U))) ? 2U : ((Channel) == (0x1UL << (6U))) ? 3U : ((Channel) == (0x1UL << (8U))) ? 4U : ((Channel) == (0x1UL << (10U))) ? 5U : ((Channel) == (0x1UL << (12U))) ? 6U : ((Channel) == (0x1UL << (14U))) ? 7U : ((Channel) == (0x1UL << (16U))) ? 8U : 9U);
  const volatile uint32_t *pReg = (volatile uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  uint32_t bitfield = (0x1UL << (2U)) << SHIFT_TAB_OCxx[iChannel];
  return ((((*pReg) & (bitfield)) == bitfield) ? 1UL : 0UL);
}


















 
static __inline void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
  uint8_t iChannel = (((Channel) == (0x1UL << (0U))) ? 0U : ((Channel) == (0x1UL << (2U))) ? 1U : ((Channel) == (0x1UL << (4U))) ? 2U : ((Channel) == (0x1UL << (6U))) ? 3U : ((Channel) == (0x1UL << (8U))) ? 4U : ((Channel) == (0x1UL << (10U))) ? 5U : ((Channel) == (0x1UL << (12U))) ? 6U : ((Channel) == (0x1UL << (14U))) ? 7U : ((Channel) == (0x1UL << (16U))) ? 8U : 9U);
  volatile uint32_t *pReg = (volatile uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  ((*pReg) |= (((0x1UL << (3U)) << SHIFT_TAB_OCxx[iChannel])));
}


















 
static __inline void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
  uint8_t iChannel = (((Channel) == (0x1UL << (0U))) ? 0U : ((Channel) == (0x1UL << (2U))) ? 1U : ((Channel) == (0x1UL << (4U))) ? 2U : ((Channel) == (0x1UL << (6U))) ? 3U : ((Channel) == (0x1UL << (8U))) ? 4U : ((Channel) == (0x1UL << (10U))) ? 5U : ((Channel) == (0x1UL << (12U))) ? 6U : ((Channel) == (0x1UL << (14U))) ? 7U : ((Channel) == (0x1UL << (16U))) ? 8U : 9U);
  volatile uint32_t *pReg = (volatile uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  ((*pReg) &= ~(((0x1UL << (3U)) << SHIFT_TAB_OCxx[iChannel])));
}


















 
static __inline uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
  uint8_t iChannel = (((Channel) == (0x1UL << (0U))) ? 0U : ((Channel) == (0x1UL << (2U))) ? 1U : ((Channel) == (0x1UL << (4U))) ? 2U : ((Channel) == (0x1UL << (6U))) ? 3U : ((Channel) == (0x1UL << (8U))) ? 4U : ((Channel) == (0x1UL << (10U))) ? 5U : ((Channel) == (0x1UL << (12U))) ? 6U : ((Channel) == (0x1UL << (14U))) ? 7U : ((Channel) == (0x1UL << (16U))) ? 8U : 9U);
  const volatile uint32_t *pReg = (volatile uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  uint32_t bitfield = (0x1UL << (3U)) << SHIFT_TAB_OCxx[iChannel];
  return ((((*pReg) & (bitfield)) == bitfield) ? 1UL : 0UL);
}





















 
static __inline void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
  uint8_t iChannel = (((Channel) == (0x1UL << (0U))) ? 0U : ((Channel) == (0x1UL << (2U))) ? 1U : ((Channel) == (0x1UL << (4U))) ? 2U : ((Channel) == (0x1UL << (6U))) ? 3U : ((Channel) == (0x1UL << (8U))) ? 4U : ((Channel) == (0x1UL << (10U))) ? 5U : ((Channel) == (0x1UL << (12U))) ? 6U : ((Channel) == (0x1UL << (14U))) ? 7U : ((Channel) == (0x1UL << (16U))) ? 8U : 9U);
  volatile uint32_t *pReg = (volatile uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  ((*pReg) |= (((0x1UL << (7U)) << SHIFT_TAB_OCxx[iChannel])));
}




















 
static __inline void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
  uint8_t iChannel = (((Channel) == (0x1UL << (0U))) ? 0U : ((Channel) == (0x1UL << (2U))) ? 1U : ((Channel) == (0x1UL << (4U))) ? 2U : ((Channel) == (0x1UL << (6U))) ? 3U : ((Channel) == (0x1UL << (8U))) ? 4U : ((Channel) == (0x1UL << (10U))) ? 5U : ((Channel) == (0x1UL << (12U))) ? 6U : ((Channel) == (0x1UL << (14U))) ? 7U : ((Channel) == (0x1UL << (16U))) ? 8U : 9U);
  volatile uint32_t *pReg = (volatile uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  ((*pReg) &= ~(((0x1UL << (7U)) << SHIFT_TAB_OCxx[iChannel])));
}






















 
static __inline uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
  uint8_t iChannel = (((Channel) == (0x1UL << (0U))) ? 0U : ((Channel) == (0x1UL << (2U))) ? 1U : ((Channel) == (0x1UL << (4U))) ? 2U : ((Channel) == (0x1UL << (6U))) ? 3U : ((Channel) == (0x1UL << (8U))) ? 4U : ((Channel) == (0x1UL << (10U))) ? 5U : ((Channel) == (0x1UL << (12U))) ? 6U : ((Channel) == (0x1UL << (14U))) ? 7U : ((Channel) == (0x1UL << (16U))) ? 8U : 9U);
  const volatile uint32_t *pReg = (volatile uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  uint32_t bitfield = (0x1UL << (7U)) << SHIFT_TAB_OCxx[iChannel];
  return ((((*pReg) & (bitfield)) == bitfield) ? 1UL : 0UL);
}











 
static __inline void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
{
  (((TIMx->BDTR)) = ((((((TIMx->BDTR))) & (~((0xFFUL << (0U))))) | (DeadTime))));
}













 
static __inline void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
{
  ((TIMx->CCR1) = (CompareValue));
}













 
static __inline void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
{
  ((TIMx->CCR2) = (CompareValue));
}













 
static __inline void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
{
  ((TIMx->CCR3) = (CompareValue));
}













 
static __inline void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
{
  ((TIMx->CCR4) = (CompareValue));
}










 
static __inline void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
{
  (((TIMx->CCR5)) = ((((((TIMx->CCR5))) & (~((0xFFFFFFFFUL << (0U))))) | (CompareValue))));
}










 
static __inline void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
{
  ((TIMx->CCR6) = (CompareValue));
}












 
static __inline uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
{
  return (uint32_t)(((TIMx->CCR1)));
}












 
static __inline uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
{
  return (uint32_t)(((TIMx->CCR2)));
}












 
static __inline uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
{
  return (uint32_t)(((TIMx->CCR3)));
}












 
static __inline uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
{
  return (uint32_t)(((TIMx->CCR4)));
}









 
static __inline uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
{
  return (uint32_t)(((TIMx->CCR5) & ((0xFFFFFFFFUL << (0U)))));
}









 
static __inline uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
{
  return (uint32_t)(((TIMx->CCR6)));
}















 
static __inline void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
{
  (((TIMx->CCR5)) = ((((((TIMx->CCR5))) & (~(((0x1UL << (31U)) | (0x1UL << (30U)) | (0x1UL << (29U)))))) | (GroupCH5))));
}


















 
static __inline void LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef *TIMx, uint32_t PulseWidthPrescaler)
{
  (((TIMx->ECR)) = ((((((TIMx->ECR))) & (~((0x7UL << (24U))))) | (PulseWidthPrescaler))));
}

















 
static __inline uint32_t LL_TIM_OC_GetPulseWidthPrescaler(TIM_TypeDef *TIMx)
{
  return (uint32_t)(((TIMx->ECR) & ((0x7UL << (24U)))));
}










 
static __inline void LL_TIM_OC_SetPulseWidth(TIM_TypeDef *TIMx, uint32_t PulseWidth)
{
  (((TIMx->ECR)) = ((((((TIMx->ECR))) & (~((0xFFUL << (16U))))) | (PulseWidth << (16U)))));
}









 
static __inline uint32_t LL_TIM_OC_GetPulseWidth(TIM_TypeDef *TIMx)
{
  return (uint32_t)(((TIMx->ECR) & ((0xFFUL << (16U)))));
}



 



 


































 
static __inline void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
{
  uint8_t iChannel = (((Channel) == (0x1UL << (0U))) ? 0U : ((Channel) == (0x1UL << (2U))) ? 1U : ((Channel) == (0x1UL << (4U))) ? 2U : ((Channel) == (0x1UL << (6U))) ? 3U : ((Channel) == (0x1UL << (8U))) ? 4U : ((Channel) == (0x1UL << (10U))) ? 5U : ((Channel) == (0x1UL << (12U))) ? 6U : ((Channel) == (0x1UL << (14U))) ? 7U : ((Channel) == (0x1UL << (16U))) ? 8U : 9U);
  volatile uint32_t *pReg = (volatile uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  (((*pReg)) = ((((((*pReg))) & (~((((0xFUL << (4U)) | (0x3UL << (2U)) | (0x3UL << (0U))) << SHIFT_TAB_ICxx[iChannel])))) | (((Configuration >> 16U) & ((0xFUL << (4U)) | (0x3UL << (2U)) | (0x3UL << (0U)))) << SHIFT_TAB_ICxx[iChannel]))));


  (((TIMx->CCER)) = ((((((TIMx->CCER))) & (~((((0x1UL << (3U)) | (0x1UL << (1U))) << SHIFT_TAB_CCxP[iChannel])))) | ((Configuration & ((0x1UL << (3U)) | (0x1UL << (1U)))) << SHIFT_TAB_CCxP[iChannel]))));

}


















 
static __inline void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
{
  uint8_t iChannel = (((Channel) == (0x1UL << (0U))) ? 0U : ((Channel) == (0x1UL << (2U))) ? 1U : ((Channel) == (0x1UL << (4U))) ? 2U : ((Channel) == (0x1UL << (6U))) ? 3U : ((Channel) == (0x1UL << (8U))) ? 4U : ((Channel) == (0x1UL << (10U))) ? 5U : ((Channel) == (0x1UL << (12U))) ? 6U : ((Channel) == (0x1UL << (14U))) ? 7U : ((Channel) == (0x1UL << (16U))) ? 8U : 9U);
  volatile uint32_t *pReg = (volatile uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  (((*pReg)) = ((((((*pReg))) & (~((((0x3UL << (0U))) << SHIFT_TAB_ICxx[iChannel])))) | ((ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]))));
}

















 
static __inline uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
{
  uint8_t iChannel = (((Channel) == (0x1UL << (0U))) ? 0U : ((Channel) == (0x1UL << (2U))) ? 1U : ((Channel) == (0x1UL << (4U))) ? 2U : ((Channel) == (0x1UL << (6U))) ? 3U : ((Channel) == (0x1UL << (8U))) ? 4U : ((Channel) == (0x1UL << (10U))) ? 5U : ((Channel) == (0x1UL << (12U))) ? 6U : ((Channel) == (0x1UL << (14U))) ? 7U : ((Channel) == (0x1UL << (16U))) ? 8U : 9U);
  const volatile uint32_t *pReg = (volatile uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  return ((((*pReg) & ((((0x3UL << (0U))) << SHIFT_TAB_ICxx[iChannel]))) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}



















 
static __inline void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
{
  uint8_t iChannel = (((Channel) == (0x1UL << (0U))) ? 0U : ((Channel) == (0x1UL << (2U))) ? 1U : ((Channel) == (0x1UL << (4U))) ? 2U : ((Channel) == (0x1UL << (6U))) ? 3U : ((Channel) == (0x1UL << (8U))) ? 4U : ((Channel) == (0x1UL << (10U))) ? 5U : ((Channel) == (0x1UL << (12U))) ? 6U : ((Channel) == (0x1UL << (14U))) ? 7U : ((Channel) == (0x1UL << (16U))) ? 8U : 9U);
  volatile uint32_t *pReg = (volatile uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  (((*pReg)) = ((((((*pReg))) & (~((((0x3UL << (2U))) << SHIFT_TAB_ICxx[iChannel])))) | ((ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]))));
}


















 
static __inline uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
{
  uint8_t iChannel = (((Channel) == (0x1UL << (0U))) ? 0U : ((Channel) == (0x1UL << (2U))) ? 1U : ((Channel) == (0x1UL << (4U))) ? 2U : ((Channel) == (0x1UL << (6U))) ? 3U : ((Channel) == (0x1UL << (8U))) ? 4U : ((Channel) == (0x1UL << (10U))) ? 5U : ((Channel) == (0x1UL << (12U))) ? 6U : ((Channel) == (0x1UL << (14U))) ? 7U : ((Channel) == (0x1UL << (16U))) ? 8U : 9U);
  const volatile uint32_t *pReg = (volatile uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  return ((((*pReg) & ((((0x3UL << (2U))) << SHIFT_TAB_ICxx[iChannel]))) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}































 
static __inline void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
{
  uint8_t iChannel = (((Channel) == (0x1UL << (0U))) ? 0U : ((Channel) == (0x1UL << (2U))) ? 1U : ((Channel) == (0x1UL << (4U))) ? 2U : ((Channel) == (0x1UL << (6U))) ? 3U : ((Channel) == (0x1UL << (8U))) ? 4U : ((Channel) == (0x1UL << (10U))) ? 5U : ((Channel) == (0x1UL << (12U))) ? 6U : ((Channel) == (0x1UL << (14U))) ? 7U : ((Channel) == (0x1UL << (16U))) ? 8U : 9U);
  volatile uint32_t *pReg = (volatile uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  (((*pReg)) = ((((((*pReg))) & (~((((0xFUL << (4U))) << SHIFT_TAB_ICxx[iChannel])))) | ((ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]))));
}






























 
static __inline uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
{
  uint8_t iChannel = (((Channel) == (0x1UL << (0U))) ? 0U : ((Channel) == (0x1UL << (2U))) ? 1U : ((Channel) == (0x1UL << (4U))) ? 2U : ((Channel) == (0x1UL << (6U))) ? 3U : ((Channel) == (0x1UL << (8U))) ? 4U : ((Channel) == (0x1UL << (10U))) ? 5U : ((Channel) == (0x1UL << (12U))) ? 6U : ((Channel) == (0x1UL << (14U))) ? 7U : ((Channel) == (0x1UL << (16U))) ? 8U : 9U);
  const volatile uint32_t *pReg = (volatile uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
  return ((((*pReg) & ((((0xFUL << (4U))) << SHIFT_TAB_ICxx[iChannel]))) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}






















 
static __inline void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
{
  uint8_t iChannel = (((Channel) == (0x1UL << (0U))) ? 0U : ((Channel) == (0x1UL << (2U))) ? 1U : ((Channel) == (0x1UL << (4U))) ? 2U : ((Channel) == (0x1UL << (6U))) ? 3U : ((Channel) == (0x1UL << (8U))) ? 4U : ((Channel) == (0x1UL << (10U))) ? 5U : ((Channel) == (0x1UL << (12U))) ? 6U : ((Channel) == (0x1UL << (14U))) ? 7U : ((Channel) == (0x1UL << (16U))) ? 8U : 9U);
  (((TIMx->CCER)) = ((((((TIMx->CCER))) & (~((((0x1UL << (3U)) | (0x1UL << (1U))) << SHIFT_TAB_CCxP[iChannel])))) | (ICPolarity << SHIFT_TAB_CCxP[iChannel]))));

}





















 
static __inline uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
{
  uint8_t iChannel = (((Channel) == (0x1UL << (0U))) ? 0U : ((Channel) == (0x1UL << (2U))) ? 1U : ((Channel) == (0x1UL << (4U))) ? 2U : ((Channel) == (0x1UL << (6U))) ? 3U : ((Channel) == (0x1UL << (8U))) ? 4U : ((Channel) == (0x1UL << (10U))) ? 5U : ((Channel) == (0x1UL << (12U))) ? 6U : ((Channel) == (0x1UL << (14U))) ? 7U : ((Channel) == (0x1UL << (16U))) ? 8U : 9U);
  return (((TIMx->CCER) & ((((0x1UL << (3U)) | (0x1UL << (1U))) << SHIFT_TAB_CCxP[iChannel]))) >>
          SHIFT_TAB_CCxP[iChannel]);
}








 
static __inline void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
{
  ((TIMx->CR2) |= ((0x1UL << (7U))));
}








 
static __inline void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
{
  ((TIMx->CR2) &= ~((0x1UL << (7U))));
}








 
static __inline uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
{
  return ((((TIMx->CR2) & ((0x1UL << (7U)))) == ((0x1UL << (7U)))) ? 1UL : 0UL);
}












 
static __inline uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
{
  return (uint32_t)(((TIMx->CCR1)));
}












 
static __inline uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
{
  return (uint32_t)(((TIMx->CCR2)));
}












 
static __inline uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
{
  return (uint32_t)(((TIMx->CCR3)));
}












 
static __inline uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
{
  return (uint32_t)(((TIMx->CCR4)));
}



 



 








 
static __inline void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
{
  ((TIMx->SMCR) |= ((0x1UL << (14U))));
}








 
static __inline void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
{
  ((TIMx->SMCR) &= ~((0x1UL << (14U))));
}








 
static __inline uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
{
  return ((((TIMx->SMCR) & ((0x1UL << (14U)))) == ((0x1UL << (14U)))) ? 1UL : 0UL);
}



















 
static __inline void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
{
  (((TIMx->SMCR)) = ((((((TIMx->SMCR))) & (~((0x10007UL << (0U)) | (0x1UL << (14U))))) | (ClockSource))));
}


















 
static __inline void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
{
  (((TIMx->SMCR)) = ((((((TIMx->SMCR))) & (~((0x10007UL << (0U))))) | (EncoderMode))));
}



 



 

















 
static __inline void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
{
  (((TIMx->CR2)) = ((((((TIMx->CR2))) & (~((0x200007UL << (4U))))) | (TimerSynchronization))));
}

























 
static __inline void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
{
  (((TIMx->CR2)) = ((((((TIMx->CR2))) & (~((0xFUL << (20U))))) | (ADCSynchronization))));
}















 
static __inline void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
{
  (((TIMx->SMCR)) = ((((((TIMx->SMCR))) & (~((0x10007UL << (0U))))) | (SlaveMode))));
}

























 
static __inline void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
{
  (((TIMx->SMCR)) = ((((((TIMx->SMCR))) & (~((0x30007UL << (4U))))) | (TriggerInput))));
}








 
static __inline void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
{
  ((TIMx->SMCR) |= ((0x1UL << (7U))));
}








 
static __inline void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
{
  ((TIMx->SMCR) &= ~((0x1UL << (7U))));
}








 
static __inline uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
{
  return ((((TIMx->SMCR) & ((0x1UL << (7U)))) == ((0x1UL << (7U)))) ? 1UL : 0UL);
}



































 
static __inline void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
                                      uint32_t ETRFilter)
{
  (((TIMx->SMCR)) = ((((((TIMx->SMCR))) & (~((0x1UL << (15U)) | (0x3UL << (12U)) | (0xFUL << (8U))))) | (ETRPolarity | ETRPrescaler | ETRFilter))));
}


























































































































 
static __inline void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
{
  (((TIMx->AF1)) = ((((((TIMx->AF1))) & (~((0xFUL << (14U))))) | (ETRSource))));
}








 
static __inline void LL_TIM_EnableSMSPreload(TIM_TypeDef *TIMx)
{
  ((TIMx->SMCR) |= ((0x1UL << (24U))));
}








 
static __inline void LL_TIM_DisableSMSPreload(TIM_TypeDef *TIMx)
{
  ((TIMx->SMCR) &= ~((0x1UL << (24U))));
}








 
static __inline uint32_t LL_TIM_IsEnabledSMSPreload(TIM_TypeDef *TIMx)
{
  return ((((TIMx->SMCR) & ((0x1UL << (24U)))) == ((0x1UL << (24U)))) ? 1UL : 0UL);
}











 
static __inline void LL_TIM_SetSMSPreloadSource(TIM_TypeDef *TIMx, uint32_t PreloadSource)
{
  (((TIMx->SMCR)) = ((((((TIMx->SMCR))) & (~((0x1UL << (25U))))) | (PreloadSource))));
}










 
static __inline uint32_t LL_TIM_GetSMSPreloadSource(TIM_TypeDef *TIMx)
{
  return (uint32_t)(((TIMx->SMCR) & ((0x1UL << (25U)))));
}



 



 







 
static __inline void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
{
  ((TIMx->BDTR) |= ((0x1UL << (12U))));
}








 
static __inline void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
{
  ((TIMx->BDTR) &= ~((0x1UL << (12U))));
}










































 
static __inline void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
                                      uint32_t BreakAFMode)
{
  (((TIMx->BDTR)) = ((((((TIMx->BDTR))) & (~((0x1UL << (13U)) | (0xFUL << (16U)) | (0x1UL << (28U))))) | (BreakPolarity | BreakFilter | BreakAFMode))));
}










 
static __inline void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
{
  ((TIMx->BDTR) |= ((0x1UL << (26U))));
}







 
static __inline void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx)
{
  ((TIMx->BDTR) &= ~((0x1UL << (26U))));
}








 
static __inline void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
{
  ((TIMx->BDTR) |= ((0x1UL << (24U))));
}








 
static __inline void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
{
  ((TIMx->BDTR) &= ~((0x1UL << (24U))));
}










































 
static __inline void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
                                       uint32_t Break2AFMode)
{
  (((TIMx->BDTR)) = ((((((TIMx->BDTR))) & (~((0x1UL << (25U)) | (0xFUL << (20U)) | (0x1UL << (29U))))) | (Break2Polarity | Break2Filter | Break2AFMode))));
}










 
static __inline void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
{
  ((TIMx->BDTR) |= ((0x1UL << (27U))));
}







 
static __inline void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx)
{
  ((TIMx->BDTR) &= ~((0x1UL << (27U))));
}















 
static __inline void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
{
  (((TIMx->BDTR)) = ((((((TIMx->BDTR))) & (~((0x1UL << (10U)) | (0x1UL << (11U))))) | (OffStateIdle | OffStateRun))));
}








 
static __inline void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
{
  ((TIMx->BDTR) |= ((0x1UL << (14U))));
}








 
static __inline void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
{
  ((TIMx->BDTR) &= ~((0x1UL << (14U))));
}








 
static __inline uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
{
  return ((((TIMx->BDTR) & ((0x1UL << (14U)))) == ((0x1UL << (14U)))) ? 1UL : 0UL);
}










 
static __inline void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
{
  ((TIMx->BDTR) |= ((0x1UL << (15U))));
}










 
static __inline void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
{
  ((TIMx->BDTR) &= ~((0x1UL << (15U))));
}








 
static __inline uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
{
  return ((((TIMx->BDTR) & ((0x1UL << (15U)))) == ((0x1UL << (15U)))) ? 1UL : 0UL);
}





































 
static __inline void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
{
  volatile uint32_t *pReg = (volatile uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
  ((*pReg) |= (Source));
}





































 
static __inline void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
{
  volatile uint32_t *pReg = (volatile uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
  ((*pReg) &= ~(Source));
}





























 
static __inline void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
                                                        uint32_t Polarity)
{
  volatile uint32_t *pReg = (volatile uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
  (((*pReg)) = ((((((*pReg))) & (~(((0x1UL << (9U)) << ((__clz(__rbit(Source))) & 0x1FUL))))) | ((Polarity << ((__clz(__rbit(Source))) & 0x1FUL))))));
}







 
static __inline void LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
{
  ((TIMx->DTR2) |= ((0x1UL << (16U))));
}








 
static __inline void LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
{
  ((TIMx->DTR2) &= ~((0x1UL << (16U))));
}








 
static __inline uint32_t LL_TIM_IsEnabledAsymmetricalDeadTime(TIM_TypeDef *TIMx)
{
  return ((((TIMx->DTR2) & ((0x1UL << (16U)))) == ((0x1UL << (16U)))) ? 1UL : 0UL);
}













 
static __inline void LL_TIM_SetFallingDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
{
  (((TIMx->DTR2)) = ((((((TIMx->DTR2))) & (~((0xFFUL << (0U))))) | (DeadTime))));
}











 
static __inline uint32_t LL_TIM_GetFallingDeadTime(TIM_TypeDef *TIMx)
{
  return (uint32_t)(((TIMx->DTR2) & ((0xFFUL << (0U)))));
}








 
static __inline void LL_TIM_EnableDeadTimePreload(TIM_TypeDef *TIMx)
{
  ((TIMx->DTR2) |= ((0x1UL << (17U))));
}








 
static __inline void LL_TIM_DisableDeadTimePreload(TIM_TypeDef *TIMx)
{
  ((TIMx->DTR2) &= ~((0x1UL << (17U))));
}








 
static __inline uint32_t LL_TIM_IsEnabledDeadTimePreload(TIM_TypeDef *TIMx)
{
  return ((((TIMx->DTR2) & ((0x1UL << (17U)))) == ((0x1UL << (17U)))) ? 1UL : 0UL);
}



 



 































































 
static __inline void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
{
  (((TIMx->DCR)) = ((((((TIMx->DCR))) & (~(((0x1FUL << (8U)) | (0x1FUL << (0U)))))) | ((DMABurstBaseAddress | DMABurstLength)))));
}



 



 








 
static __inline void LL_TIM_EnableEncoderIndex(TIM_TypeDef *TIMx)
{
  ((TIMx->ECR) |= ((0x1UL << (0U))));
}








 
static __inline void LL_TIM_DisableEncoderIndex(TIM_TypeDef *TIMx)
{
  ((TIMx->ECR) &= ~((0x1UL << (0U))));
}








 
static __inline uint32_t LL_TIM_IsEnabledEncoderIndex(TIM_TypeDef *TIMx)
{
  return ((((TIMx->ECR) & ((0x1UL << (0U)))) == ((0x1UL << (0U)))) ? 1U : 0U);
}












 
static __inline void LL_TIM_SetIndexDirection(TIM_TypeDef *TIMx, uint32_t IndexDirection)
{
  (((TIMx->ECR)) = ((((((TIMx->ECR))) & (~((0x3UL << (1U))))) | (IndexDirection))));
}











 
static __inline uint32_t LL_TIM_GetIndexDirection(TIM_TypeDef *TIMx)
{
  return (uint32_t)(((TIMx->ECR) & ((0x3UL << (1U)))));
}








 
static __inline void LL_TIM_EnableFirstIndex(TIM_TypeDef *TIMx)
{
  ((TIMx->ECR) |= ((0x1UL << (5U))));
}








 
static __inline void LL_TIM_DisableFirstIndex(TIM_TypeDef *TIMx)
{
  ((TIMx->ECR) &= ~((0x1UL << (5U))));
}








 
static __inline uint32_t LL_TIM_IsEnabledFirstIndex(TIM_TypeDef *TIMx)
{
  return ((((TIMx->ECR) & ((0x1UL << (5U)))) == ((0x1UL << (5U)))) ? 1UL : 0UL);
}















 
static __inline void LL_TIM_SetIndexPositionning(TIM_TypeDef *TIMx, uint32_t IndexPositionning)
{
  (((TIMx->ECR)) = ((((((TIMx->ECR))) & (~((0x3UL << (6U))))) | (IndexPositionning))));
}














 
static __inline uint32_t LL_TIM_GetIndexPositionning(TIM_TypeDef *TIMx)
{
  return (uint32_t)(((TIMx->ECR) & ((0x3UL << (6U)))));
}














 
static __inline void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration)
{
  (((TIMx->ECR)) = ((((((TIMx->ECR))) & (~((0x3UL << (1U)) | (0x1UL << (5U)) | (0x3UL << (6U))))) | (Configuration))));
}



 



 













































































































































































































 
static __inline void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
{
  (((TIMx->TISEL)) = ((((((TIMx->TISEL))) & (~(((0xFUL << (0U)) | (0xFUL << (8U)) | (0xFUL << (16U)) | (0xFUL << (24U)))))) | (Remap))));
}







 
static __inline void LL_TIM_EnableHSE32(TIM_TypeDef *TIMx)
{
  ((TIMx->OR) |= ((0x1UL << (0U))));
}







 
static __inline void LL_TIM_DisableHSE32(TIM_TypeDef *TIMx)
{
  ((TIMx->OR) &= ~((0x1UL << (0U))));
}







 
static __inline uint32_t LL_TIM_IsEnabledHSE32(TIM_TypeDef *TIMx)
{
  return ((((TIMx->OR) & ((0x1UL << (0U)))) == ((0x1UL << (0U)))) ? 1UL : 0UL);
}



 



 





















 
static __inline void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
{
  (((TIMx->SMCR)) = ((((((TIMx->SMCR))) & (~((0x1UL << (3U))))) | (((OCRefClearInputSource & (0x1U << (28U))) >> (28U)) << (3U)))));

  (((TIMx->AF2)) = ((((((TIMx->AF2))) & (~((0x7UL << (16U))))) | (OCRefClearInputSource))));
}


 



 





 
static __inline void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
{
  ((TIMx->SR) = (~((0x1UL << (0U)))));
}






 
static __inline uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
{
  return ((((TIMx->SR) & ((0x1UL << (0U)))) == ((0x1UL << (0U)))) ? 1UL : 0UL);
}






 
static __inline void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
{
  ((TIMx->SR) = (~((0x1UL << (1U)))));
}






 
static __inline uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
{
  return ((((TIMx->SR) & ((0x1UL << (1U)))) == ((0x1UL << (1U)))) ? 1UL : 0UL);
}






 
static __inline void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
{
  ((TIMx->SR) = (~((0x1UL << (2U)))));
}






 
static __inline uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
{
  return ((((TIMx->SR) & ((0x1UL << (2U)))) == ((0x1UL << (2U)))) ? 1UL : 0UL);
}






 
static __inline void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
{
  ((TIMx->SR) = (~((0x1UL << (3U)))));
}






 
static __inline uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
{
  return ((((TIMx->SR) & ((0x1UL << (3U)))) == ((0x1UL << (3U)))) ? 1UL : 0UL);
}






 
static __inline void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
{
  ((TIMx->SR) = (~((0x1UL << (4U)))));
}






 
static __inline uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
{
  return ((((TIMx->SR) & ((0x1UL << (4U)))) == ((0x1UL << (4U)))) ? 1UL : 0UL);
}






 
static __inline void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
{
  ((TIMx->SR) = (~((0x1UL << (16U)))));
}






 
static __inline uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
{
  return ((((TIMx->SR) & ((0x1UL << (16U)))) == ((0x1UL << (16U)))) ? 1UL : 0UL);
}






 
static __inline void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
{
  ((TIMx->SR) = (~((0x1UL << (17U)))));
}






 
static __inline uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
{
  return ((((TIMx->SR) & ((0x1UL << (17U)))) == ((0x1UL << (17U)))) ? 1UL : 0UL);
}






 
static __inline void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
{
  ((TIMx->SR) = (~((0x1UL << (5U)))));
}






 
static __inline uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
{
  return ((((TIMx->SR) & ((0x1UL << (5U)))) == ((0x1UL << (5U)))) ? 1UL : 0UL);
}






 
static __inline void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
{
  ((TIMx->SR) = (~((0x1UL << (6U)))));
}






 
static __inline uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
{
  return ((((TIMx->SR) & ((0x1UL << (6U)))) == ((0x1UL << (6U)))) ? 1UL : 0UL);
}






 
static __inline void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
{
  ((TIMx->SR) = (~((0x1UL << (7U)))));
}






 
static __inline uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
{
  return ((((TIMx->SR) & ((0x1UL << (7U)))) == ((0x1UL << (7U)))) ? 1UL : 0UL);
}






 
static __inline void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
{
  ((TIMx->SR) = (~((0x1UL << (8U)))));
}






 
static __inline uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
{
  return ((((TIMx->SR) & ((0x1UL << (8U)))) == ((0x1UL << (8U)))) ? 1UL : 0UL);
}






 
static __inline void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
{
  ((TIMx->SR) = (~((0x1UL << (9U)))));
}







 
static __inline uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
{
  return ((((TIMx->SR) & ((0x1UL << (9U)))) == ((0x1UL << (9U)))) ? 1UL : 0UL);
}






 
static __inline void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
{
  ((TIMx->SR) = (~((0x1UL << (10U)))));
}







 
static __inline uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
{
  return ((((TIMx->SR) & ((0x1UL << (10U)))) == ((0x1UL << (10U)))) ? 1UL : 0UL);
}






 
static __inline void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
{
  ((TIMx->SR) = (~((0x1UL << (11U)))));
}







 
static __inline uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
{
  return ((((TIMx->SR) & ((0x1UL << (11U)))) == ((0x1UL << (11U)))) ? 1UL : 0UL);
}






 
static __inline void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
{
  ((TIMx->SR) = (~((0x1UL << (12U)))));
}







 
static __inline uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
{
  return ((((TIMx->SR) & ((0x1UL << (12U)))) == ((0x1UL << (12U)))) ? 1UL : 0UL);
}






 
static __inline void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
{
  ((TIMx->SR) = (~((0x1UL << (13U)))));
}






 
static __inline uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx)
{
  return ((((TIMx->SR) & ((0x1UL << (13U)))) == ((0x1UL << (13U)))) ? 1UL : 0UL);
}








 
static __inline void LL_TIM_ClearFlag_TERR(TIM_TypeDef *TIMx)
{
  ((TIMx->SR) = (~((0x1UL << (23U)))));
}








 
static __inline uint32_t LL_TIM_IsActiveFlag_TERR(TIM_TypeDef *TIMx)
{
  return ((((TIMx->SR) & ((0x1UL << (23U)))) == ((0x1UL << (23U)))) ? 1UL : 0UL);
}








 
static __inline void LL_TIM_ClearFlag_IERR(TIM_TypeDef *TIMx)
{
  ((TIMx->SR) = (~((0x1UL << (22U)))));
}








 
static __inline uint32_t LL_TIM_IsActiveFlag_IERR(TIM_TypeDef *TIMx)
{
  return ((((TIMx->SR) & ((0x1UL << (22U)))) == ((0x1UL << (22U)))) ? 1UL : 0UL);
}








 
static __inline void LL_TIM_ClearFlag_DIR(TIM_TypeDef *TIMx)
{
  ((TIMx->SR) = (~((0x1UL << (21U)))));
}








 
static __inline uint32_t LL_TIM_IsActiveFlag_DIR(TIM_TypeDef *TIMx)
{
  return ((((TIMx->SR) & ((0x1UL << (21U)))) == ((0x1UL << (21U)))) ? 1UL : 0UL);
}








 
static __inline void LL_TIM_ClearFlag_IDX(TIM_TypeDef *TIMx)
{
  ((TIMx->SR) = (~((0x1UL << (20U)))));
}








 
static __inline uint32_t LL_TIM_IsActiveFlag_IDX(TIM_TypeDef *TIMx)
{
  return ((((TIMx->SR) & ((0x1UL << (20U)))) == ((0x1UL << (20U)))) ? 1UL : 0UL);
}


 



 





 
static __inline void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) |= ((0x1UL << (0U))));
}






 
static __inline void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) &= ~((0x1UL << (0U))));
}






 
static __inline uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
{
  return ((((TIMx->DIER) & ((0x1UL << (0U)))) == ((0x1UL << (0U)))) ? 1UL : 0UL);
}






 
static __inline void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) |= ((0x1UL << (1U))));
}






 
static __inline void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) &= ~((0x1UL << (1U))));
}






 
static __inline uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
{
  return ((((TIMx->DIER) & ((0x1UL << (1U)))) == ((0x1UL << (1U)))) ? 1UL : 0UL);
}






 
static __inline void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) |= ((0x1UL << (2U))));
}






 
static __inline void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) &= ~((0x1UL << (2U))));
}






 
static __inline uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
{
  return ((((TIMx->DIER) & ((0x1UL << (2U)))) == ((0x1UL << (2U)))) ? 1UL : 0UL);
}






 
static __inline void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) |= ((0x1UL << (3U))));
}






 
static __inline void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) &= ~((0x1UL << (3U))));
}






 
static __inline uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
{
  return ((((TIMx->DIER) & ((0x1UL << (3U)))) == ((0x1UL << (3U)))) ? 1UL : 0UL);
}






 
static __inline void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) |= ((0x1UL << (4U))));
}






 
static __inline void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) &= ~((0x1UL << (4U))));
}






 
static __inline uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
{
  return ((((TIMx->DIER) & ((0x1UL << (4U)))) == ((0x1UL << (4U)))) ? 1UL : 0UL);
}






 
static __inline void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) |= ((0x1UL << (5U))));
}






 
static __inline void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) &= ~((0x1UL << (5U))));
}






 
static __inline uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
{
  return ((((TIMx->DIER) & ((0x1UL << (5U)))) == ((0x1UL << (5U)))) ? 1UL : 0UL);
}






 
static __inline void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) |= ((0x1UL << (6U))));
}






 
static __inline void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) &= ~((0x1UL << (6U))));
}






 
static __inline uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
{
  return ((((TIMx->DIER) & ((0x1UL << (6U)))) == ((0x1UL << (6U)))) ? 1UL : 0UL);
}






 
static __inline void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) |= ((0x1UL << (7U))));
}






 
static __inline void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) &= ~((0x1UL << (7U))));
}






 
static __inline uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
{
  return ((((TIMx->DIER) & ((0x1UL << (7U)))) == ((0x1UL << (7U)))) ? 1UL : 0UL);
}








 
static __inline void LL_TIM_EnableIT_TERR(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) |= ((0x1UL << (23U))));
}








 
static __inline void LL_TIM_DisableIT_TERR(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) &= ~((0x1UL << (23U))));
}








 
static __inline uint32_t LL_TIM_IsEnabledIT_TERR(TIM_TypeDef *TIMx)
{
  return ((((TIMx->DIER) & ((0x1UL << (23U)))) == ((0x1UL << (23U)))) ? 1UL : 0UL);
}








 
static __inline void LL_TIM_EnableIT_IERR(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) |= ((0x1UL << (22U))));
}








 
static __inline void LL_TIM_DisableIT_IERR(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) &= ~((0x1UL << (22U))));
}








 
static __inline uint32_t LL_TIM_IsEnabledIT_IERR(TIM_TypeDef *TIMx)
{
  return ((((TIMx->DIER) & ((0x1UL << (22U)))) == ((0x1UL << (22U)))) ? 1UL : 0UL);
}








 
static __inline void LL_TIM_EnableIT_DIR(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) |= ((0x1UL << (21U))));
}








 
static __inline void LL_TIM_DisableIT_DIR(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) &= ~((0x1UL << (21U))));
}








 
static __inline uint32_t LL_TIM_IsEnabledIT_DIR(TIM_TypeDef *TIMx)
{
  return ((((TIMx->DIER) & ((0x1UL << (21U)))) == ((0x1UL << (21U)))) ? 1UL : 0UL);
}








 
static __inline void LL_TIM_EnableIT_IDX(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) |= ((0x1UL << (20U))));
}








 
static __inline void LL_TIM_DisableIT_IDX(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) &= ~((0x1UL << (20U))));
}








 
static __inline uint32_t LL_TIM_IsEnabledIT_IDX(TIM_TypeDef *TIMx)
{
  return ((((TIMx->DIER) & ((0x1UL << (20U)))) == ((0x1UL << (20U)))) ? 1UL : 0UL);
}



 



 





 
static __inline void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) |= ((0x1UL << (8U))));
}






 
static __inline void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) &= ~((0x1UL << (8U))));
}






 
static __inline uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
{
  return ((((TIMx->DIER) & ((0x1UL << (8U)))) == ((0x1UL << (8U)))) ? 1UL : 0UL);
}






 
static __inline void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) |= ((0x1UL << (9U))));
}






 
static __inline void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) &= ~((0x1UL << (9U))));
}






 
static __inline uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
{
  return ((((TIMx->DIER) & ((0x1UL << (9U)))) == ((0x1UL << (9U)))) ? 1UL : 0UL);
}






 
static __inline void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) |= ((0x1UL << (10U))));
}






 
static __inline void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) &= ~((0x1UL << (10U))));
}






 
static __inline uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
{
  return ((((TIMx->DIER) & ((0x1UL << (10U)))) == ((0x1UL << (10U)))) ? 1UL : 0UL);
}






 
static __inline void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) |= ((0x1UL << (11U))));
}






 
static __inline void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) &= ~((0x1UL << (11U))));
}






 
static __inline uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
{
  return ((((TIMx->DIER) & ((0x1UL << (11U)))) == ((0x1UL << (11U)))) ? 1UL : 0UL);
}






 
static __inline void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) |= ((0x1UL << (12U))));
}






 
static __inline void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) &= ~((0x1UL << (12U))));
}






 
static __inline uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
{
  return ((((TIMx->DIER) & ((0x1UL << (12U)))) == ((0x1UL << (12U)))) ? 1UL : 0UL);
}






 
static __inline void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) |= ((0x1UL << (13U))));
}






 
static __inline void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) &= ~((0x1UL << (13U))));
}






 
static __inline uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
{
  return ((((TIMx->DIER) & ((0x1UL << (13U)))) == ((0x1UL << (13U)))) ? 1UL : 0UL);
}






 
static __inline void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) |= ((0x1UL << (14U))));
}






 
static __inline void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
{
  ((TIMx->DIER) &= ~((0x1UL << (14U))));
}






 
static __inline uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
{
  return ((((TIMx->DIER) & ((0x1UL << (14U)))) == ((0x1UL << (14U)))) ? 1UL : 0UL);
}



 



 





 
static __inline void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
{
  ((TIMx->EGR) |= ((0x1UL << (0U))));
}






 
static __inline void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
{
  ((TIMx->EGR) |= ((0x1UL << (1U))));
}






 
static __inline void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
{
  ((TIMx->EGR) |= ((0x1UL << (2U))));
}






 
static __inline void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
{
  ((TIMx->EGR) |= ((0x1UL << (3U))));
}






 
static __inline void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
{
  ((TIMx->EGR) |= ((0x1UL << (4U))));
}






 
static __inline void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
{
  ((TIMx->EGR) |= ((0x1UL << (5U))));
}






 
static __inline void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
{
  ((TIMx->EGR) |= ((0x1UL << (6U))));
}






 
static __inline void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
{
  ((TIMx->EGR) |= ((0x1UL << (7U))));
}






 
static __inline void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
{
  ((TIMx->EGR) |= ((0x1UL << (8U))));
}



 




 

ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);


 




 



 





 





#line 46 "../Core/Inc/main.h"
#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usart.h"
















 

 







 
#line 29 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usart.h"



 





 

 
 


 
 
static const uint32_t USART_PRESCALER_TAB[] =
{
  1UL,
  2UL,
  4UL,
  6UL,
  8UL,
  10UL,
  12UL,
  16UL,
  32UL,
  64UL,
  128UL,
  256UL
};


 

 
 



 


 


 



 



 
typedef struct
{
  uint32_t PrescalerValue;            



 

  uint32_t BaudRate;                  


 

  uint32_t DataWidth;                 



 

  uint32_t StopBits;                  



 

  uint32_t Parity;                    



 

  uint32_t TransferDirection;         



 

  uint32_t HardwareFlowControl;       



 

  uint32_t OverSampling;              



 

} LL_USART_InitTypeDef;



 
typedef struct
{
  uint32_t ClockOutput;               




 

  uint32_t ClockPolarity;             




 

  uint32_t ClockPhase;                




 

  uint32_t LastBitClockPulse;         





 

} LL_USART_ClockInitTypeDef;



 


 


 




 
#line 201 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usart.h"


 




 
#line 237 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usart.h"


 




 
#line 262 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usart.h"


 



 
#line 275 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usart.h"


 



 






 



 





 



 




 



 





 



 




 




 





 




 




 



 




 



 




 



 
#line 382 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usart.h"


 



 






 



 




 



 




 



 




 



 




 



 




 



 






 



 




 



 






 



 





 



 




 



 




 



 




 



 




 



 

 


 



 







 







 



 



 




















 























 






 



 

 



 



 






 
static __inline void LL_USART_Enable(USART_TypeDef *USARTx)
{
  ((USARTx->CR1) |= ((0x1UL << (0U))));
}









 
static __inline void LL_USART_Disable(USART_TypeDef *USARTx)
{
  ((USARTx->CR1) &= ~((0x1UL << (0U))));
}






 
static __inline uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR1) & ((0x1UL << (0U)))) == ((0x1UL << (0U)))) ? 1UL : 0UL);
}








 
static __inline void LL_USART_EnableFIFO(USART_TypeDef *USARTx)
{
  ((USARTx->CR1) |= ((0x1UL << (29U))));
}








 
static __inline void LL_USART_DisableFIFO(USART_TypeDef *USARTx)
{
  ((USARTx->CR1) &= ~((0x1UL << (29U))));
}








 
static __inline uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR1) & ((0x1UL << (29U)))) == ((0x1UL << (29U)))) ? 1UL : 0UL);
}















 
static __inline void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
{
  do { uint32_t val; do { val = (_Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR3))) _Pragma("pop") & ~((0x7UL << (29U)))) | (Threshold << (29U)); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR3)) _Pragma("pop")) != 0U); } while(0);
}














 
static __inline uint32_t LL_USART_GetTXFIFOThreshold(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->CR3) & ((0x7UL << (29U)))) >> (29U));
}















 
static __inline void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
{
  do { uint32_t val; do { val = (_Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR3))) _Pragma("pop") & ~((0x7UL << (25U)))) | (Threshold << (25U)); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR3)) _Pragma("pop")) != 0U); } while(0);
}














 
static __inline uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->CR3) & ((0x7UL << (25U)))) >> (25U));
}























 
static __inline void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
{
  do { uint32_t val; do { val = (_Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR3))) _Pragma("pop") & ~((0x7UL << (29U)) | (0x7UL << (25U)))) | ((TXThreshold << (29U)) | (RXThreshold << (25U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR3)) _Pragma("pop")) != 0U); } while(0);

}










 
static __inline void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR1))) _Pragma("pop") | ((0x1UL << (1U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR1)) _Pragma("pop")) != 0U); } while(0);
}









 
static __inline void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR1))) _Pragma("pop") & ~((0x1UL << (1U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR1)) _Pragma("pop")) != 0U); } while(0);
}








 
static __inline uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR1) & ((0x1UL << (1U)))) == ((0x1UL << (1U)))) ? 1UL : 0UL);
}






 
static __inline void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR1))) _Pragma("pop") | ((0x1UL << (2U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR1)) _Pragma("pop")) != 0U); } while(0);
}






 
static __inline void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR1))) _Pragma("pop") & ~((0x1UL << (2U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR1)) _Pragma("pop")) != 0U); } while(0);
}






 
static __inline void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR1))) _Pragma("pop") | ((0x1UL << (3U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR1)) _Pragma("pop")) != 0U); } while(0);
}






 
static __inline void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR1))) _Pragma("pop") & ~((0x1UL << (3U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR1)) _Pragma("pop")) != 0U); } while(0);
}













 
static __inline void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
{
  do { uint32_t val; do { val = (_Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR1))) _Pragma("pop") & ~((0x1UL << (2U)) | (0x1UL << (3U)))) | (TransferDirection); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR1)) _Pragma("pop")) != 0U); } while(0);
}











 
static __inline uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->CR1) & ((0x1UL << (2U)) | (0x1UL << (3U)))));
}














 
static __inline void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
{
  (((USARTx->CR1)) = ((((((USARTx->CR1))) & (~((0x1UL << (9U)) | (0x1UL << (10U))))) | (Parity))));
}










 
static __inline uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->CR1) & ((0x1UL << (9U)) | (0x1UL << (10U)))));
}









 
static __inline void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
{
  (((USARTx->CR1)) = ((((((USARTx->CR1))) & (~((0x1UL << (11U))))) | (Method))));
}








 
static __inline uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->CR1) & ((0x1UL << (11U)))));
}











 
static __inline void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
{
  (((USARTx->CR1)) = ((((((USARTx->CR1))) & (~((0x10001UL << (12U))))) | (DataWidth))));
}










 
static __inline uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->CR1) & ((0x10001UL << (12U)))));
}






 
static __inline void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR1))) _Pragma("pop") | ((0x1UL << (13U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR1)) _Pragma("pop")) != 0U); } while(0);
}






 
static __inline void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR1))) _Pragma("pop") & ~((0x1UL << (13U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR1)) _Pragma("pop")) != 0U); } while(0);
}






 
static __inline uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR1) & ((0x1UL << (13U)))) == ((0x1UL << (13U)))) ? 1UL : 0UL);
}









 
static __inline void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
{
  (((USARTx->CR1)) = ((((((USARTx->CR1))) & (~((0x1UL << (15U))))) | (OverSampling))));
}








 
static __inline uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->CR1) & ((0x1UL << (15U)))));
}











 
static __inline void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
{
  (((USARTx->CR2)) = ((((((USARTx->CR2))) & (~((0x1UL << (8U))))) | (LastBitClockPulse))));
}











 
static __inline uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->CR2) & ((0x1UL << (8U)))));
}











 
static __inline void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
{
  (((USARTx->CR2)) = ((((((USARTx->CR2))) & (~((0x1UL << (9U))))) | (ClockPhase))));
}










 
static __inline uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->CR2) & ((0x1UL << (9U)))));
}











 
static __inline void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
{
  (((USARTx->CR2)) = ((((((USARTx->CR2))) & (~((0x1UL << (10U))))) | (ClockPolarity))));
}










 
static __inline uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->CR2) & ((0x1UL << (10U)))));
}























 
static __inline void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
{
  (((USARTx->CR2)) = ((((((USARTx->CR2))) & (~((0x1UL << (9U)) | (0x1UL << (10U)) | (0x1UL << (8U))))) | (Phase | Polarity | LBCPOutput))));
}





















 
static __inline void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
{
  (((USARTx->PRESC)) = ((((((USARTx->PRESC))) & (~((0xFUL << (0U))))) | ((uint16_t)PrescalerValue))));
}




















 
static __inline uint32_t LL_USART_GetPrescaler(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->PRESC) & ((0xFUL << (0U)))));
}








 
static __inline void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
{
  ((USARTx->CR2) |= ((0x1UL << (11U))));
}








 
static __inline void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
{
  ((USARTx->CR2) &= ~((0x1UL << (11U))));
}








 
static __inline uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR2) & ((0x1UL << (11U)))) == ((0x1UL << (11U)))) ? 1UL : 0UL);
}











 
static __inline void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
{
  (((USARTx->CR2)) = ((((((USARTx->CR2))) & (~((0x3UL << (12U))))) | (StopBits))));
}










 
static __inline uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->CR2) & ((0x3UL << (12U)))));
}



























 
static __inline void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
                                              uint32_t StopBits)
{
  (((USARTx->CR1)) = ((((((USARTx->CR1))) & (~((0x1UL << (9U)) | (0x1UL << (10U)) | (0x10001UL << (12U))))) | (Parity | DataWidth))));
  (((USARTx->CR2)) = ((((((USARTx->CR2))) & (~((0x3UL << (12U))))) | (StopBits))));
}









 
static __inline void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)
{
  (((USARTx->CR2)) = ((((((USARTx->CR2))) & (~((0x1UL << (15U))))) | (SwapConfig))));
}








 
static __inline uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->CR2) & ((0x1UL << (15U)))));
}









 
static __inline void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
{
  (((USARTx->CR2)) = ((((((USARTx->CR2))) & (~((0x1UL << (16U))))) | (PinInvMethod))));
}








 
static __inline uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->CR2) & ((0x1UL << (16U)))));
}









 
static __inline void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
{
  (((USARTx->CR2)) = ((((((USARTx->CR2))) & (~((0x1UL << (17U))))) | (PinInvMethod))));
}








 
static __inline uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->CR2) & ((0x1UL << (17U)))));
}











 
static __inline void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)
{
  (((USARTx->CR2)) = ((((((USARTx->CR2))) & (~((0x1UL << (18U))))) | (DataLogic))));
}








 
static __inline uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->CR2) & ((0x1UL << (18U)))));
}











 
static __inline void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)
{
  (((USARTx->CR2)) = ((((((USARTx->CR2))) & (~((0x1UL << (19U))))) | (BitOrder))));
}










 
static __inline uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->CR2) & ((0x1UL << (19U)))));
}








 
static __inline void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
{
  ((USARTx->CR2) |= ((0x1UL << (20U))));
}








 
static __inline void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
{
  ((USARTx->CR2) &= ~((0x1UL << (20U))));
}








 
static __inline uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR2) & ((0x1UL << (20U)))) == ((0x1UL << (20U)))) ? 1UL : 0UL);
}













 
static __inline void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
{
  (((USARTx->CR2)) = ((((((USARTx->CR2))) & (~((0x3UL << (21U))))) | (AutoBaudRateMode))));
}












 
static __inline uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->CR2) & ((0x3UL << (21U)))));
}






 
static __inline void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)
{
  ((USARTx->CR2) |= ((0x1UL << (23U))));
}






 
static __inline void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
{
  ((USARTx->CR2) &= ~((0x1UL << (23U))));
}






 
static __inline uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR2) & ((0x1UL << (23U)))) == ((0x1UL << (23U)))) ? 1UL : 0UL);
}























 
static __inline void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
{
  (((USARTx->CR2)) = ((((((USARTx->CR2))) & (~((0xFFUL << (24U)) | (0x1UL << (4U))))) | ((uint32_t)(AddressLen | (NodeAddress << (24U)))))));

}










 
static __inline uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->CR2) & ((0xFFUL << (24U)))) >> (24U));
}








 
static __inline uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->CR2) & ((0x1UL << (4U)))));
}








 
static __inline void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
{
  ((USARTx->CR3) |= ((0x1UL << (8U))));
}








 
static __inline void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
{
  ((USARTx->CR3) &= ~((0x1UL << (8U))));
}








 
static __inline void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
{
  ((USARTx->CR3) |= ((0x1UL << (9U))));
}








 
static __inline void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
{
  ((USARTx->CR3) &= ~((0x1UL << (9U))));
}














 
static __inline void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
{
  (((USARTx->CR3)) = ((((((USARTx->CR3))) & (~((0x1UL << (8U)) | (0x1UL << (9U))))) | (HardwareFlowControl))));
}













 
static __inline uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->CR3) & ((0x1UL << (8U)) | (0x1UL << (9U)))));
}






 
static __inline void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
{
  ((USARTx->CR3) |= ((0x1UL << (11U))));
}






 
static __inline void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
{
  ((USARTx->CR3) &= ~((0x1UL << (11U))));
}






 
static __inline uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR3) & ((0x1UL << (11U)))) == ((0x1UL << (11U)))) ? 1UL : 0UL);
}






 
static __inline void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)
{
  ((USARTx->CR3) &= ~((0x1UL << (12U))));
}






 
static __inline void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
{
  ((USARTx->CR3) |= ((0x1UL << (12U))));
}






 
static __inline uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR3) & ((0x1UL << (12U)))) != (0x1UL << (12U))) ? 1UL : 0UL);
}












 
static __inline void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
{
  (((USARTx->CR3)) = ((((((USARTx->CR3))) & (~((0x3UL << (20U))))) | (Type))));
}











 
static __inline uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->CR3) & ((0x3UL << (20U)))));
}





























 
static __inline void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
                                          uint32_t OverSampling,
                                          uint32_t BaudRate)
{
  uint32_t usartdiv;
  uint32_t brrtemp;

  if (PrescalerValue > ((0x8UL << (0U)) | (0x2UL << (0U)) | (0x1UL << (0U))))
  {
     
  }
  else if (BaudRate == 0U)
  {
     
  }
  else if (OverSampling == (0x1UL << (15U)))
  {
    usartdiv = (uint16_t)((((((PeriphClk)/(USART_PRESCALER_TAB[((uint8_t)PrescalerValue)]))*2U) + ((BaudRate)/2U))/(BaudRate)));
    brrtemp = usartdiv & 0xFFF0U;
    brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
    USARTx->BRR = brrtemp;
  }
  else
  {
    USARTx->BRR = (uint16_t)(((((PeriphClk)/(USART_PRESCALER_TAB[((uint8_t)PrescalerValue)])) + ((BaudRate)/2U))/(BaudRate)));
  }
}


























 
static __inline uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
                                              uint32_t OverSampling)
{
  uint32_t usartdiv;
  uint32_t brrresult = 0x0U;
  uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue]));

  usartdiv = USARTx->BRR;

  if (usartdiv == 0U)
  {
     
  }
  else if (OverSampling == (0x1UL << (15U)))
  {
    usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
    if (usartdiv != 0U)
    {
      brrresult = (periphclkpresc * 2U) / usartdiv;
    }
  }
  else
  {
    if ((usartdiv & 0xFFFFU) != 0U)
    {
      brrresult = periphclkpresc / usartdiv;
    }
  }
  return (brrresult);
}







 
static __inline void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout)
{
  (((USARTx->RTOR)) = ((((((USARTx->RTOR))) & (~((0xFFFFFFUL << (0U))))) | (Timeout))));
}






 
static __inline uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->RTOR) & ((0xFFFFFFUL << (0U)))));
}







 
static __inline void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)
{
  (((USARTx->RTOR)) = ((((((USARTx->RTOR))) & (~((0xFFUL << (24U))))) | (BlockLength << (24U)))));
}






 
static __inline uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->RTOR) & ((0xFFUL << (24U)))) >> (24U));
}



 



 








 
static __inline void LL_USART_EnableIrda(USART_TypeDef *USARTx)
{
  ((USARTx->CR3) |= ((0x1UL << (1U))));
}








 
static __inline void LL_USART_DisableIrda(USART_TypeDef *USARTx)
{
  ((USARTx->CR3) &= ~((0x1UL << (1U))));
}








 
static __inline uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR3) & ((0x1UL << (1U)))) == ((0x1UL << (1U)))) ? 1UL : 0UL);
}











 
static __inline void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
{
  (((USARTx->CR3)) = ((((((USARTx->CR3))) & (~((0x1UL << (2U))))) | (PowerMode))));
}










 
static __inline uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->CR3) & ((0x1UL << (2U)))));
}










 
static __inline void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
{
  (((USARTx->GTPR)) = ((((((USARTx->GTPR))) & (~((0xFFUL << (0U))))) | ((uint16_t)PrescalerValue))));
}









 
static __inline uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->GTPR) & ((0xFFUL << (0U)))));
}



 



 








 
static __inline void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
{
  ((USARTx->CR3) |= ((0x1UL << (4U))));
}








 
static __inline void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
{
  ((USARTx->CR3) &= ~((0x1UL << (4U))));
}








 
static __inline uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR3) & ((0x1UL << (4U)))) == ((0x1UL << (4U)))) ? 1UL : 0UL);
}








 
static __inline void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
{
  ((USARTx->CR3) |= ((0x1UL << (5U))));
}








 
static __inline void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
{
  ((USARTx->CR3) &= ~((0x1UL << (5U))));
}








 
static __inline uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR3) & ((0x1UL << (5U)))) == ((0x1UL << (5U)))) ? 1UL : 0UL);
}














 
static __inline void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount)
{
  (((USARTx->CR3)) = ((((((USARTx->CR3))) & (~((0x7UL << (17U))))) | (AutoRetryCount << (17U)))));
}








 
static __inline uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->CR3) & ((0x7UL << (17U)))) >> (17U));
}










 
static __inline void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
{
  (((USARTx->GTPR)) = ((((((USARTx->GTPR))) & (~((0xFFUL << (0U))))) | ((uint16_t)PrescalerValue))));
}









 
static __inline uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->GTPR) & ((0xFFUL << (0U)))));
}










 
static __inline void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
{
  (((USARTx->GTPR)) = ((((((USARTx->GTPR))) & (~((0xFFUL << (8U))))) | ((uint16_t)(GuardTime << (8U))))));
}









 
static __inline uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->GTPR) & ((0xFFUL << (8U)))) >> (8U));
}



 



 








 
static __inline void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
{
  ((USARTx->CR3) |= ((0x1UL << (3U))));
}








 
static __inline void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
{
  ((USARTx->CR3) &= ~((0x1UL << (3U))));
}








 
static __inline uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR3) & ((0x1UL << (3U)))) == ((0x1UL << (3U)))) ? 1UL : 0UL);
}



 



 







 
static __inline void LL_USART_EnableSPISlave(USART_TypeDef *USARTx)
{
  ((USARTx->CR2) |= ((0x1UL << (0U))));
}








 
static __inline void LL_USART_DisableSPISlave(USART_TypeDef *USARTx)
{
  ((USARTx->CR2) &= ~((0x1UL << (0U))));
}








 
static __inline uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR2) & ((0x1UL << (0U)))) == ((0x1UL << (0U)))) ? 1UL : 0UL);
}










 
static __inline void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx)
{
  ((USARTx->CR2) &= ~((0x1UL << (3U))));
}









 
static __inline void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx)
{
  ((USARTx->CR2) |= ((0x1UL << (3U))));
}








 
static __inline uint32_t LL_USART_IsEnabledSPISlaveSelect(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR2) & ((0x1UL << (3U)))) != ((0x1UL << (3U)))) ? 1UL : 0UL);
}



 



 











 
static __inline void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
{
  (((USARTx->CR2)) = ((((((USARTx->CR2))) & (~((0x1UL << (5U))))) | (LINBDLength))));
}










 
static __inline uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->CR2) & ((0x1UL << (5U)))));
}








 
static __inline void LL_USART_EnableLIN(USART_TypeDef *USARTx)
{
  ((USARTx->CR2) |= ((0x1UL << (14U))));
}








 
static __inline void LL_USART_DisableLIN(USART_TypeDef *USARTx)
{
  ((USARTx->CR2) &= ~((0x1UL << (14U))));
}








 
static __inline uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR2) & ((0x1UL << (14U)))) == ((0x1UL << (14U)))) ? 1UL : 0UL);
}



 



 









 
static __inline void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)
{
  (((USARTx->CR1)) = ((((((USARTx->CR1))) & (~((0x1FUL << (16U))))) | (Time << (16U)))));
}








 
static __inline uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->CR1) & ((0x1FUL << (16U)))) >> (16U));
}









 
static __inline void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)
{
  (((USARTx->CR1)) = ((((((USARTx->CR1))) & (~((0x1FUL << (21U))))) | (Time << (21U)))));
}








 
static __inline uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->CR1) & ((0x1FUL << (21U)))) >> (21U));
}








 
static __inline void LL_USART_EnableDEMode(USART_TypeDef *USARTx)
{
  ((USARTx->CR3) |= ((0x1UL << (14U))));
}








 
static __inline void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
{
  ((USARTx->CR3) &= ~((0x1UL << (14U))));
}








 
static __inline uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR3) & ((0x1UL << (14U)))) == ((0x1UL << (14U)))) ? 1UL : 0UL);
}











 
static __inline void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity)
{
  (((USARTx->CR3)) = ((((((USARTx->CR3))) & (~((0x1UL << (15U))))) | (Polarity))));
}










 
static __inline uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx)
{
  return (uint32_t)(((USARTx->CR3) & ((0x1UL << (15U)))));
}



 



 

























 
static __inline void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
{
  


 
  ((USARTx->CR2) &= ~(((0x1UL << (14U)) | (0x1UL << (11U)))));
  ((USARTx->CR3) &= ~(((0x1UL << (5U)) | (0x1UL << (1U)) | (0x1UL << (3U)))));
}



























 
static __inline void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
{
  


 
  ((USARTx->CR2) &= ~(((0x1UL << (14U)))));
  ((USARTx->CR3) &= ~(((0x1UL << (5U)) | (0x1UL << (1U)) | (0x1UL << (3U)))));
   
  ((USARTx->CR2) |= ((0x1UL << (11U))));
}





























 
static __inline void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
{
  


 
  ((USARTx->CR2) &= ~(((0x1UL << (11U)) | (0x3UL << (12U)))));
  ((USARTx->CR3) &= ~(((0x1UL << (1U)) | (0x1UL << (5U)) | (0x1UL << (3U)))));
   
  ((USARTx->CR2) |= ((0x1UL << (14U))));
}



























 
static __inline void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
{
  


 
  ((USARTx->CR2) &= ~(((0x1UL << (14U)) | (0x1UL << (11U)))));
  ((USARTx->CR3) &= ~(((0x1UL << (5U)) | (0x1UL << (1U)))));
   
  ((USARTx->CR3) |= ((0x1UL << (3U))));
}





























 
static __inline void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
{
  


 
  ((USARTx->CR2) &= ~(((0x1UL << (14U)))));
  ((USARTx->CR3) &= ~(((0x1UL << (1U)) | (0x1UL << (3U)))));
   
   
  ((USARTx->CR2) |= (((0x1UL << (12U)) | (0x2UL << (12U)) | (0x1UL << (11U)))));
   
  ((USARTx->CR3) |= ((0x1UL << (5U))));
}





























 
static __inline void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
{
  


 
  ((USARTx->CR2) &= ~(((0x1UL << (14U)) | (0x1UL << (11U)) | (0x3UL << (12U)))));
  ((USARTx->CR3) &= ~(((0x1UL << (5U)) | (0x1UL << (3U)))));
   
  ((USARTx->CR3) |= ((0x1UL << (1U))));
}



























 
static __inline void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
{
  


 
  ((USARTx->CR2) &= ~(((0x1UL << (14U)) | (0x1UL << (11U)))));
  ((USARTx->CR3) &= ~(((0x1UL << (5U)) | (0x1UL << (3U)) | (0x1UL << (1U)))));
}



 



 






 
static __inline uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
{
  return ((((USARTx->ISR) & ((0x1UL << (0U)))) == ((0x1UL << (0U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
{
  return ((((USARTx->ISR) & ((0x1UL << (1U)))) == ((0x1UL << (1U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
{
  return ((((USARTx->ISR) & ((0x1UL << (2U)))) == ((0x1UL << (2U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
{
  return ((((USARTx->ISR) & ((0x1UL << (3U)))) == ((0x1UL << (3U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
{
  return ((((USARTx->ISR) & ((0x1UL << (4U)))) == ((0x1UL << (4U)))) ? 1UL : 0UL);
}

 









 
static __inline uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx)
{
  return ((((USARTx->ISR) & ((0x1UL << (5U)))) == ((0x1UL << (5U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
{
  return ((((USARTx->ISR) & ((0x1UL << (6U)))) == ((0x1UL << (6U)))) ? 1UL : 0UL);
}

 









 
static __inline uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx)
{
  return ((((USARTx->ISR) & ((0x1UL << (7U)))) == ((0x1UL << (7U)))) ? 1UL : 0UL);
}








 
static __inline uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
{
  return ((((USARTx->ISR) & ((0x1UL << (8U)))) == ((0x1UL << (8U)))) ? 1UL : 0UL);
}








 
static __inline uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
{
  return ((((USARTx->ISR) & ((0x1UL << (9U)))) == ((0x1UL << (9U)))) ? 1UL : 0UL);
}








 
static __inline uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)
{
  return ((((USARTx->ISR) & ((0x1UL << (10U)))) == ((0x1UL << (10U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
{
  return ((((USARTx->ISR) & ((0x1UL << (11U)))) == ((0x1UL << (11U)))) ? 1UL : 0UL);
}








 
static __inline uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
{
  return ((((USARTx->ISR) & ((0x1UL << (12U)))) == ((0x1UL << (12U)))) ? 1UL : 0UL);
}








 
static __inline uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx)
{
  return ((((USARTx->ISR) & ((0x1UL << (13U)))) == ((0x1UL << (13U)))) ? 1UL : 0UL);
}








 
static __inline uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
{
  return ((((USARTx->ISR) & ((0x1UL << (14U)))) == ((0x1UL << (14U)))) ? 1UL : 0UL);
}








 
static __inline uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)
{
  return ((((USARTx->ISR) & ((0x1UL << (15U)))) == ((0x1UL << (15U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)
{
  return ((((USARTx->ISR) & ((0x1UL << (16U)))) == ((0x1UL << (16U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)
{
  return ((((USARTx->ISR) & ((0x1UL << (17U)))) == ((0x1UL << (17U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
{
  return ((((USARTx->ISR) & ((0x1UL << (18U)))) == ((0x1UL << (18U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
{
  return ((((USARTx->ISR) & ((0x1UL << (19U)))) == ((0x1UL << (19U)))) ? 1UL : 0UL);
}








 
static __inline uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)
{
  return ((((USARTx->ISR) & ((0x1UL << (20U)))) == ((0x1UL << (20U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
{
  return ((((USARTx->ISR) & ((0x1UL << (21U)))) == ((0x1UL << (21U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)
{
  return ((((USARTx->ISR) & ((0x1UL << (22U)))) == ((0x1UL << (22U)))) ? 1UL : 0UL);
}








 
static __inline uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx)
{
  return ((((USARTx->ISR) & ((0x1UL << (23U)))) == ((0x1UL << (23U)))) ? 1UL : 0UL);
}








 
static __inline uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx)
{
  return ((((USARTx->ISR) & ((0x1UL << (24U)))) == ((0x1UL << (24U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx)
{
  return ((((USARTx->ISR) & ((0x1UL << (25U)))) == ((0x1UL << (25U)))) ? 1UL : 0UL);
}








 
static __inline uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx)
{
  return ((((USARTx->ISR) & ((0x1UL << (27U)))) == ((0x1UL << (27U)))) ? 1UL : 0UL);
}








 
static __inline uint32_t LL_USART_IsActiveFlag_RXFT(USART_TypeDef *USARTx)
{
  return ((((USARTx->ISR) & ((0x1UL << (26U)))) == ((0x1UL << (26U)))) ? 1UL : 0UL);
}






 
static __inline void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
{
  ((USARTx->ICR) = ((0x1UL << (0U))));
}






 
static __inline void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
{
  ((USARTx->ICR) = ((0x1UL << (1U))));
}






 
static __inline void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
{
  ((USARTx->ICR) = ((0x1UL << (2U))));
}






 
static __inline void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
{
  ((USARTx->ICR) = ((0x1UL << (3U))));
}






 
static __inline void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
{
  ((USARTx->ICR) = ((0x1UL << (4U))));
}








 
static __inline void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx)
{
  ((USARTx->ICR) = ((0x1UL << (5U))));
}






 
static __inline void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
{
  ((USARTx->ICR) = ((0x1UL << (6U))));
}






 
static __inline void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx)
{
  ((USARTx->ICR) = ((0x1UL << (7U))));
}








 
static __inline void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
{
  ((USARTx->ICR) = ((0x1UL << (8U))));
}








 
static __inline void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
{
  ((USARTx->ICR) = ((0x1UL << (9U))));
}






 
static __inline void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)
{
  ((USARTx->ICR) = ((0x1UL << (11U))));
}








 
static __inline void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)
{
  ((USARTx->ICR) = ((0x1UL << (12U))));
}








 
static __inline void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx)
{
  ((USARTx->ICR) = ((0x1UL << (13U))));
}






 
static __inline void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
{
  ((USARTx->ICR) = ((0x1UL << (17U))));
}








 
static __inline void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)
{
  ((USARTx->ICR) = ((0x1UL << (20U))));
}



 



 






 
static __inline void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR1))) _Pragma("pop") | ((0x1UL << (4U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR1)) _Pragma("pop")) != 0U); } while(0);
}

 









 
static __inline void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR1))) _Pragma("pop") | ((0x1UL << (5U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR1)) _Pragma("pop")) != 0U); } while(0);
}






 
static __inline void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR1))) _Pragma("pop") | ((0x1UL << (6U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR1)) _Pragma("pop")) != 0U); } while(0);
}

 









 
static __inline void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR1))) _Pragma("pop") | ((0x1UL << (7U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR1)) _Pragma("pop")) != 0U); } while(0);
}






 
static __inline void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR1))) _Pragma("pop") | ((0x1UL << (8U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR1)) _Pragma("pop")) != 0U); } while(0);
}






 
static __inline void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR1))) _Pragma("pop") | ((0x1UL << (14U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR1)) _Pragma("pop")) != 0U); } while(0);
}






 
static __inline void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR1))) _Pragma("pop") | ((0x1UL << (26U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR1)) _Pragma("pop")) != 0U); } while(0);
}








 
static __inline void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR1))) _Pragma("pop") | ((0x1UL << (27U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR1)) _Pragma("pop")) != 0U); } while(0);
}








 
static __inline void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR1))) _Pragma("pop") | ((0x1UL << (30U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR1)) _Pragma("pop")) != 0U); } while(0);
}






 
static __inline void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR1))) _Pragma("pop") | ((0x1UL << (31U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR1)) _Pragma("pop")) != 0U); } while(0);
}








 
static __inline void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
{
  ((USARTx->CR2) |= ((0x1UL << (6U))));
}










 
static __inline void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR3))) _Pragma("pop") | ((0x1UL << (0U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR3)) _Pragma("pop")) != 0U); } while(0);
}








 
static __inline void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR3))) _Pragma("pop") | ((0x1UL << (10U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR3)) _Pragma("pop")) != 0U); } while(0);
}








 
static __inline void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR3))) _Pragma("pop") | ((0x1UL << (22U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR3)) _Pragma("pop")) != 0U); } while(0);
}








 
static __inline void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR3))) _Pragma("pop") | ((0x1UL << (23U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR3)) _Pragma("pop")) != 0U); } while(0);
}








 
static __inline void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR3))) _Pragma("pop") | ((0x1UL << (24U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR3)) _Pragma("pop")) != 0U); } while(0);
}








 
static __inline void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR3))) _Pragma("pop") | ((0x1UL << (28U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR3)) _Pragma("pop")) != 0U); } while(0);
}






 
static __inline void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR1))) _Pragma("pop") & ~((0x1UL << (4U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR1)) _Pragma("pop")) != 0U); } while(0);
}

 









 
static __inline void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR1))) _Pragma("pop") & ~((0x1UL << (5U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR1)) _Pragma("pop")) != 0U); } while(0);
}






 
static __inline void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR1))) _Pragma("pop") & ~((0x1UL << (6U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR1)) _Pragma("pop")) != 0U); } while(0);
}

 









 
static __inline void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR1))) _Pragma("pop") & ~((0x1UL << (7U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR1)) _Pragma("pop")) != 0U); } while(0);
}






 
static __inline void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR1))) _Pragma("pop") & ~((0x1UL << (8U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR1)) _Pragma("pop")) != 0U); } while(0);
}






 
static __inline void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR1))) _Pragma("pop") & ~((0x1UL << (14U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR1)) _Pragma("pop")) != 0U); } while(0);
}






 
static __inline void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR1))) _Pragma("pop") & ~((0x1UL << (26U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR1)) _Pragma("pop")) != 0U); } while(0);
}








 
static __inline void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR1))) _Pragma("pop") & ~((0x1UL << (27U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR1)) _Pragma("pop")) != 0U); } while(0);
}








 
static __inline void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR1))) _Pragma("pop") & ~((0x1UL << (30U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR1)) _Pragma("pop")) != 0U); } while(0);
}








 
static __inline void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR1))) _Pragma("pop") & ~((0x1UL << (31U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR1)) _Pragma("pop")) != 0U); } while(0);
}








 
static __inline void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
{
  ((USARTx->CR2) &= ~((0x1UL << (6U))));
}










 
static __inline void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR3))) _Pragma("pop") & ~((0x1UL << (0U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR3)) _Pragma("pop")) != 0U); } while(0);
}








 
static __inline void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR3))) _Pragma("pop") & ~((0x1UL << (10U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR3)) _Pragma("pop")) != 0U); } while(0);
}








 
static __inline void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR3))) _Pragma("pop") & ~((0x1UL << (22U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR3)) _Pragma("pop")) != 0U); } while(0);
}








 
static __inline void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR3))) _Pragma("pop") & ~((0x1UL << (23U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR3)) _Pragma("pop")) != 0U); } while(0);
}








 
static __inline void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR3))) _Pragma("pop") & ~((0x1UL << (24U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR3)) _Pragma("pop")) != 0U); } while(0);
}








 
static __inline void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR3))) _Pragma("pop") & ~((0x1UL << (28U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR3)) _Pragma("pop")) != 0U); } while(0);
}






 
static __inline uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR1) & ((0x1UL << (4U)))) == ((0x1UL << (4U)))) ? 1UL : 0UL);
}

 









 
static __inline uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR1) & ((0x1UL << (5U)))) == ((0x1UL << (5U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR1) & ((0x1UL << (6U)))) == ((0x1UL << (6U)))) ? 1UL : 0UL);
}

 









 
static __inline uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR1) & ((0x1UL << (7U)))) == ((0x1UL << (7U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR1) & ((0x1UL << (8U)))) == ((0x1UL << (8U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR1) & ((0x1UL << (14U)))) == ((0x1UL << (14U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR1) & ((0x1UL << (26U)))) == ((0x1UL << (26U)))) ? 1UL : 0UL);
}








 
static __inline uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR1) & ((0x1UL << (27U)))) == ((0x1UL << (27U)))) ? 1UL : 0UL);
}








 
static __inline uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR1) & ((0x1UL << (30U)))) == ((0x1UL << (30U)))) ? 1UL : 0UL);
}








 
static __inline uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR1) & ((0x1UL << (31U)))) == ((0x1UL << (31U)))) ? 1UL : 0UL);
}








 
static __inline uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR2) & ((0x1UL << (6U)))) == ((0x1UL << (6U)))) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR3) & ((0x1UL << (0U)))) == ((0x1UL << (0U)))) ? 1UL : 0UL);
}








 
static __inline uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR3) & ((0x1UL << (10U)))) == ((0x1UL << (10U)))) ? 1UL : 0UL);
}








 
static __inline uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR3) & ((0x1UL << (22U)))) == ((0x1UL << (22U)))) ? 1UL : 0UL);
}








 
static __inline uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR3) & ((0x1UL << (23U)))) == ((0x1UL << (23U)))) ? 1UL : 0UL);
}








 
static __inline uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR3) & ((0x1UL << (24U)))) == ((0x1UL << (24U)))) ? 1UL : 0UL);
}








 
static __inline uint32_t LL_USART_IsEnabledIT_RXFT(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR3) & ((0x1UL << (28U)))) == ((0x1UL << (28U)))) ? 1UL : 0UL);
}



 



 






 
static __inline void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR3))) _Pragma("pop") | ((0x1UL << (6U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR3)) _Pragma("pop")) != 0U); } while(0);
}






 
static __inline void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR3))) _Pragma("pop") & ~((0x1UL << (6U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR3)) _Pragma("pop")) != 0U); } while(0);
}






 
static __inline uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR3) & ((0x1UL << (6U)))) == ((0x1UL << (6U)))) ? 1UL : 0UL);
}






 
static __inline void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR3))) _Pragma("pop") | ((0x1UL << (7U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR3)) _Pragma("pop")) != 0U); } while(0);
}






 
static __inline void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
{
  do { uint32_t val; do { val = _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex((volatile uint32_t *)&(USARTx->CR3))) _Pragma("pop") & ~((0x1UL << (7U))); } while ((_Pragma("push") _Pragma("diag_suppress 3731") __strex(val, (volatile uint32_t *)&(USARTx->CR3)) _Pragma("pop")) != 0U); } while(0);
}






 
static __inline uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR3) & ((0x1UL << (7U)))) == ((0x1UL << (7U)))) ? 1UL : 0UL);
}






 
static __inline void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx)
{
  ((USARTx->CR3) |= ((0x1UL << (13U))));
}






 
static __inline void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
{
  ((USARTx->CR3) &= ~((0x1UL << (13U))));
}






 
static __inline uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx)
{
  return ((((USARTx->CR3) & ((0x1UL << (13U)))) == ((0x1UL << (13U)))) ? 1UL : 0UL);
}










 
static __inline uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
{
  uint32_t data_reg_addr;

  if (Direction == 0x00000000U)
  {
     
    data_reg_addr = (uint32_t) &(USARTx->TDR);
  }
  else
  {
     
    data_reg_addr = (uint32_t) &(USARTx->RDR);
  }

  return data_reg_addr;
}



 



 






 
static __inline uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
{
  return (uint8_t)(((USARTx->RDR) & ((0x1FFUL << (0U)))) & 0xFFU);
}






 
static __inline uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
{
  return (uint16_t)(((USARTx->RDR) & ((0x1FFUL << (0U)))));
}







 
static __inline void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
{
  USARTx->TDR = Value;
}







 
static __inline void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
{
  USARTx->TDR = (uint16_t)(Value & 0x1FFUL);
}



 



 








 
static __inline void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
{
  ((USARTx->RQR) |= ((uint16_t)(0x1UL << (0U))));
}






 
static __inline void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
{
  ((USARTx->RQR) |= ((uint16_t)(0x1UL << (1U))));
}






 
static __inline void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
{
  ((USARTx->RQR) |= ((uint16_t)(0x1UL << (2U))));
}










 
static __inline void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
{
  ((USARTx->RQR) |= ((uint16_t)(0x1UL << (3U))));
}








 
static __inline void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)
{
  ((USARTx->RQR) |= ((uint16_t)(0x1UL << (4U))));
}



 




 
ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
void        LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
void        LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);


 




 



 





 







#line 47 "../Core/Inc/main.h"
#line 1 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_gpio.h"
















 

 







 
#line 29 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_gpio.h"



 





 







 

 
 
 
 



 



 


 



 



 
typedef struct
{
  uint32_t Pin;          
 

  uint32_t Mode;         


 

  uint32_t Speed;        


 

  uint32_t OutputType;   


 

  uint32_t Pull;         


 

  uint32_t Alternate;    


 
} LL_GPIO_InitTypeDef;



 


 


 



 
#line 137 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_gpio.h"


 



 






 



 




 



 






 







 





 



 
#line 205 "../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_gpio.h"


 



 

 


 



 







 







 



 



 

 


 



 






























 
static __inline void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
{
  (((GPIOx->MODER)) = ((((((GPIOx->MODER))) & (~(((0x3UL << (0U)) << ((__clz(__rbit(Pin))) * 2U))))) | ((Mode << ((__clz(__rbit(Pin))) * 2U))))));
}





























 
static __inline uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
{
  return (uint32_t)(((GPIOx->MODER) & (((0x3UL << (0U)) << ((__clz(__rbit(Pin))) * 2U)))) >> ((__clz(__rbit(Pin))) * 2U));

}





























 
static __inline void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
{
  (((GPIOx->OTYPER)) = ((((((GPIOx->OTYPER))) & (~(PinMask))) | ((PinMask * OutputType)))));
}





























 
static __inline uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
{
  return (uint32_t)(((GPIOx->OTYPER) & (Pin)) >> (__clz(__rbit(Pin))));
}
































 
static __inline void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t  Speed)
{
  (((GPIOx->OSPEEDR)) = ((((((GPIOx->OSPEEDR))) & (~(((0x3UL << (0U)) << ((__clz(__rbit(Pin))) * 2U))))) | ((Speed << ((__clz(__rbit(Pin))) * 2U))))));

}































 
static __inline uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
{
  return (uint32_t)(((GPIOx->OSPEEDR) & (((0x3UL << (0U)) << ((__clz(__rbit(Pin))) * 2U)))) >> ((__clz(__rbit(Pin))) * 2U));

}




























 
static __inline void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
{
  (((GPIOx->PUPDR)) = ((((((GPIOx->PUPDR))) & (~(((0x3UL << (0U)) << ((__clz(__rbit(Pin))) * 2U))))) | ((Pull << ((__clz(__rbit(Pin))) * 2U))))));
}



























 
static __inline uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
{
  return (uint32_t)(((GPIOx->PUPDR) & (((0x3UL << (0U)) << ((__clz(__rbit(Pin))) * 2U)))) >> ((__clz(__rbit(Pin))) * 2U));

}


































 
static __inline void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
{
  (((GPIOx->AFR[0])) = ((((((GPIOx->AFR[0]))) & (~(((0xFUL << (0U)) << ((__clz(__rbit(Pin))) * 4U))))) | ((Alternate << ((__clz(__rbit(Pin))) * 4U))))));

}































 
static __inline uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
{
  return (uint32_t)(((GPIOx->AFR[0]) & (((0xFUL << (0U)) << ((__clz(__rbit(Pin))) * 4U)))) >> ((__clz(__rbit(Pin))) * 4U));

}


































 
static __inline void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
{
  (((GPIOx->AFR[1])) = ((((((GPIOx->AFR[1]))) & (~(((0xFUL << (0U)) << ((__clz(__rbit(Pin >> 8U))) * 4U))))) | ((Alternate << ((__clz(__rbit(Pin >> 8U))) * 4U))))));

}
































 
static __inline uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
{
  return (uint32_t)(((GPIOx->AFR[1]) & (((0xFUL << (0U)) << ((__clz(__rbit(Pin >> 8U))) * 4U)))) >> ((__clz(__rbit(Pin >> 8U))) * 4U));

}






























 
static __inline void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
  volatile uint32_t temp;
  ((GPIOx->LCKR) = ((0x1UL << (16U)) | PinMask));
  ((GPIOx->LCKR) = (PinMask));
  ((GPIOx->LCKR) = ((0x1UL << (16U)) | PinMask));
   
  temp = ((GPIOx->LCKR));
  (void) temp;
}
























 
static __inline uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
  return ((((GPIOx->LCKR) & (PinMask)) == (PinMask)) ? 1UL : 0UL);
}






 
static __inline uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
{
  return ((((GPIOx->LCKR) & ((0x1UL << (16U)))) == ((0x1UL << (16U)))) ? 1UL : 0UL);
}



 



 






 
static __inline uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
{
  return (uint32_t)(((GPIOx->IDR)));
}
























 
static __inline uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
  return ((((GPIOx->IDR) & (PinMask)) == (PinMask)) ? 1UL : 0UL);
}







 
static __inline void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
{
  ((GPIOx->ODR) = (PortValue));
}






 
static __inline uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
{
  return (uint32_t)(((GPIOx->ODR)));
}
























 
static __inline uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
  return ((((GPIOx->ODR) & (PinMask)) == (PinMask)) ? 1UL : 0UL);
}
























 
static __inline void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
  ((GPIOx->BSRR) = (PinMask));
}
























 
static __inline void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
  ((GPIOx->BRR) = (PinMask));
}
























 
static __inline void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
  uint32_t odr = ((GPIOx->ODR));
  ((GPIOx->BSRR) = (((odr & PinMask) << 16u) | (~odr & PinMask)));
}



 




 

ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
void        LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);



 




 



 




 







#line 48 "../Core/Inc/main.h"

 
 
#line 52 "../Core/Inc/main.h"
#line 1 "../Core/Inc/Vofa.h"
 








 
 

 







 

 
 
#line 26 "../Core/Inc/Vofa.h"
 

 
 
#line 1 "../Core/Inc/main.h"
 
















 
 

 
#line 31 "../Core/Inc/Vofa.h"
 

 
 


 

 
 

 

 

 
void VofaData_Config(uint8_t ch_count);
void VofaData_Update(uint8_t ch,float value);
void VofaData_Send(void);
 

 

 

 

extern uint8_t USART2_TX_BUFFER[];





#line 53 "../Core/Inc/main.h"
#line 1 "..\\Middlewares\\MotorControl\\foc.h"
 








 
 

 







 

 
 
#line 26 "..\\Middlewares\\MotorControl\\foc.h"
 

 
 

 

 
 

 

 
 

 

 
 

 

 
 
void foc_commutate(float theta);
 





#line 54 "../Core/Inc/main.h"
#line 1 "..\\Middlewares\\MotorControl\\foc_task.h"
 








 
 

 







 

 
 

 

 
 

 

 
 

 

 
 

 

 


 
void Peripheral_Init_Task(void);
 

 

 

 





#line 55 "../Core/Inc/main.h"
#line 1 "..\\Middlewares\\MotorControl\\IC_MU.h"
 








 
 

 







 

 
 
#line 26 "..\\Middlewares\\MotorControl\\IC_MU.h"
 

 

 
 
#line 38 "..\\Middlewares\\MotorControl\\IC_MU.h"



 







 

 
 


typedef union
{
	struct bit_status
	{
		unsigned int AM_MIN:1;
		unsigned int AM_MAX:1;
		unsigned int AN_MIN:1;
		unsigned int AN_MAX:1;
		unsigned int STUP:1;
		unsigned int reserve1:1;
		unsigned int reserve2:1;
		unsigned int reserve3:1;
	}bit;
	struct byte_status
	{
		uint8_t status0;
		uint8_t status1;
	}byte;
	uint16_t Status;
}_IC_MU_Status;

typedef struct
{
	uint16_t active_state;
	int angle;
	_IC_MU_Status Status;
}IC_MU_Data;
 

 
 

 

 
 

 

 
 
extern IC_MU_Data ICMU_Data[];
int IC_MU_Angle_Read(uint8_t type);
uint16_t IC_MU_Active(uint8_t type);
uint8_t IC_MU_Status(uint8_t type);
 







#line 56 "../Core/Inc/main.h"
#line 1 "..\\Middlewares\\MotorControl\\DriverPara.h"
 








 
 

 







 

 
 

 

 
 

 

 
 

 

 
 

 

 


 

 

 

 











 





#line 57 "../Core/Inc/main.h"
#line 1 "..\\Middlewares\\MotorControl\\Encoder.h"
 








 
 

 







 

 
 
#line 26 "..\\Middlewares\\MotorControl\\Encoder.h"
 

 
 

 

 
 

 

 
 

 

 
 
void encoder_routine(void);
 

 

 

 





#line 58 "../Core/Inc/main.h"
#line 1 "..\\Middlewares\\MotorControl\\calibration.h"
 








 
 

 







 

 
 
#line 26 "..\\Middlewares\\MotorControl\\calibration.h"
#line 1 "..\\Middlewares\\MotorControl\\structs.h"
 








 
 

 







 

 
 
#line 26 "..\\Middlewares\\MotorControl\\structs.h"
#line 1 "..\\Middlewares\\MotorControl\\calibration.h"
 








 
 

 
#line 27 "..\\Middlewares\\MotorControl\\structs.h"
 

 
 



typedef struct
{
	uint8_t pole_pairs;							
	int offset;											
	float theta_ref;								
	int start_count;								
	int count;											
	uint8_t started;								
	float time;											
	float theta_start;						  
	int ezero;
	uint8_t phase_order;						
	uint8_t done_ordering, done_cal, done_rl;		
	uint16_t sample_count;					
	float next_sample_time;					
	int error_arr[64 * 128];
	int lut_arr[128];
}CalibrationStruct;

typedef struct{
	  int i_a_offset, i_b_offset, i_c_offset;                 
    int adc1_raw, adc2_raw;                      					  
    float i_a, i_b, i_c;                                    
    float i_d, i_q, i_q_filt, i_d_filt;                     
		float i_alpha,i_beta,v_alpha,v_beta;
    float v_d, v_q;                                         
		float v_bus;                                            
    float theta_mech, theta_elec;                           
    float dtheta_mech, dtheta_elec, dtheta_elec_filt;       
    
    float i_d_ref, i_q_ref, i_d_ref_filt, i_q_ref_filt;     
    int loop_count;                                         
    int timeout;                                            
    int mode;																								
    int ovp_flag;                                           
    float p_des, v_des, kp, kd, t_ff;                       
    float v_ref, fw_int;                                     
    float cogging[128];
		int svm_sector;
} ControllerStruct;

typedef struct
{
	int last_raw;
	int raw;
	float last_angle;
	float angle;
	int linear;
	
	float angle_multi;
	
}EncoderStruct;


		
 

 
 

 

 
 

 

 
 
extern EncoderStruct MotorEncoder;
extern CalibrationStruct Calibration;
extern ControllerStruct MotorController;
 

 
 

 

 

 

 





#line 27 "..\\Middlewares\\MotorControl\\calibration.h"
 

 
 


 

 
 

 

 
 

 

 


 
void motor_encoder_calibration(EncoderStruct *encoder,ControllerStruct *controller,CalibrationStruct *cal);
 

 

 

 





#line 59 "../Core/Inc/main.h"
#line 60 "../Core/Inc/main.h"
 
#line 1 "../Core/Inc/utils_math.h"
 








 
 

 







 

 
 
#line 26 "../Core/Inc/utils_math.h"
 

 
 

 

 
 






 

 
 

 

 


 
float utils_digital_radians(int32_t number,uint32_t range);
 

 

 

 





#line 62 "../Core/Inc/main.h"


#line 1 ".\\RTE\\Compiler\\EventRecorderConf.h"







 


























#line 65 "../Core/Inc/main.h"
#line 1 "C:\\Users\\xianglei\\AppData\\Local\\Arm\\Packs\\Keil\\ARM_Compiler\\1.7.2\\Include\\EventRecorder.h"







 




#line 14 "C:\\Users\\xianglei\\AppData\\Local\\Arm\\Packs\\Keil\\ARM_Compiler\\1.7.2\\Include\\EventRecorder.h"




















#line 40 "C:\\Users\\xianglei\\AppData\\Local\\Arm\\Packs\\Keil\\ARM_Compiler\\1.7.2\\Include\\EventRecorder.h"






extern uint32_t EventRecorderTimerSetup (void);



extern uint32_t EventRecorderTimerGetFreq (void);



extern uint32_t EventRecorderTimerGetCount (void);








extern uint32_t EventRecorderInitialize (uint32_t recording, uint32_t start);






extern uint32_t EventRecorderEnable (uint32_t recording, uint32_t comp_start, uint32_t comp_end);






extern uint32_t EventRecorderDisable (uint32_t recording, uint32_t comp_start, uint32_t comp_end);



extern uint32_t EventRecorderStart (void);



extern uint32_t EventRecorderStop (void);



extern uint32_t EventRecorderClockUpdate (void);









extern uint32_t EventRecordData (uint32_t id, const void *data, uint32_t len);






extern uint32_t EventRecord2 (uint32_t id, uint32_t val1, uint32_t val2);








extern uint32_t EventRecord4 (uint32_t id, uint32_t val1, uint32_t val2, uint32_t val3, uint32_t val4);








































































#line 66 "../Core/Inc/main.h"
 

 
 

 

 
 

 

 
 

 

 
void Error_Handler(void);

 

 

 
#line 103 "../Core/Inc/main.h"
 


 





#line 22 "../Core/Src/stm32g4xx_it.c"
#line 1 "../Core/Inc/stm32g4xx_it.h"
 















 
 

 







 
 

 

 
 

 

 
 

 

 
 

 

 
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void DebugMon_Handler(void);
void DMA1_Channel1_IRQHandler(void);
void DMA1_Channel2_IRQHandler(void);
void ADC1_2_IRQHandler(void);
void FDCAN1_IT0_IRQHandler(void);
void TIM1_BRK_TIM15_IRQHandler(void);
void TIM1_UP_TIM16_IRQHandler(void);
void TIM20_UP_IRQHandler(void);
 

 





#line 23 "../Core/Src/stm32g4xx_it.c"
 
 
 

 
 

 

 
 

 

 
 

 

 
 

 

 
 

 

 
 

 

 
extern FDCAN_HandleTypeDef hfdcan1;
extern TIM_HandleTypeDef htim20;

 

 

 
 
 


 
void NMI_Handler(void)
{
   

   
   
  while (1)
  {
  }
   
}



 
void HardFault_Handler(void)
{
   

   
  while (1)
  {
     
     
  }
}



 
void MemManage_Handler(void)
{
   

   
  while (1)
  {
     
     
  }
}



 
void BusFault_Handler(void)
{
   

   
  while (1)
  {
     
     
  }
}



 
void UsageFault_Handler(void)
{
   

   
  while (1)
  {
     
     
  }
}



 
void DebugMon_Handler(void)
{
   

   
   

   
}

 
 
 
 
 
 



 
void DMA1_Channel1_IRQHandler(void)
{
   

   

   

   
}



 
void DMA1_Channel2_IRQHandler(void)
{
   

   

   

   
}
float volt1,volt2;



 
void ADC1_2_IRQHandler(void)
{
   
	if((((ADC_TypeDef *) (((0x40000000UL) + 0x08000000UL) + 0x08000000UL))->ISR & (0x1UL << (6U))) == (0x1UL << (6U)))
  {
		
    ((ADC_TypeDef *) (((0x40000000UL) + 0x08000000UL) + 0x08000000UL))->ISR = ~(0x1UL << (5U));
		
		
		LL_ADC_ClearFlag_JEOS( ((ADC_TypeDef *) (((0x40000000UL) + 0x08000000UL) + 0x08000000UL)) );
		
		
		LL_TIM_SetTriggerOutput(((TIM_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x2C00UL)), 0x00000000U);
		EventRecord2 (0xEF00U+0x00000U+(0), ((uint32_t) "../Core/Src/stm32g4xx_it.c"), 208);
		
		
		encoder_routine();
		
		motor_encoder_calibration(&MotorEncoder,&MotorController,&Calibration);
		
		
		
		EventRecord2 (0xEF20U+0x00000U+((0) & 0xFU), ((uint32_t) "../Core/Src/stm32g4xx_it.c"), 217);
		
		
		
		
		volt1 = ((ADC_TypeDef *) (((0x40000000UL) + 0x08000000UL) + 0x08000000UL))->JDR1;
		VofaData_Update(0,volt1);
		volt2 = ((ADC_TypeDef *) (((0x40000000UL) + 0x08000000UL) + 0x08000100UL))->JDR1;
		VofaData_Update(1,volt2);
		VofaData_Send();
		
		
	 }
   

   

   
}



 
void FDCAN1_IT0_IRQHandler(void)
{
   

   
  HAL_FDCAN_IRQHandler(&hfdcan1);
   

   
}



 
void TIM1_BRK_TIM15_IRQHandler(void)
{
   
	
   

   

   
}



 
void TIM1_UP_TIM16_IRQHandler(void)
{
   
	   
	LL_TIM_ClearFlag_UPDATE(((TIM_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x2C00UL)));
	


	
	
	
	LL_TIM_SetTriggerOutput(((TIM_TypeDef *) (((0x40000000UL) + 0x00010000UL) + 0x2C00UL)), ((0x000004UL << (4U)) | (0x000002UL << (4U)) | (0x000001UL << (4U))));

	
   

   

   
}



 
void TIM20_UP_IRQHandler(void)
{
   

   
  HAL_TIM_IRQHandler(&htim20);
   

   
}

 

 
